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Using the Commodore 64 as a logic analyzer

DrWatson's profile picture
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Commodore64
 · 1 year ago
Using the Commodore 64 as a logic analyzer
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When building a logic circuit, you generally also want to know what is happening inside: when a certain conductor goes to logic level "0" or "1" and when a certain flip flop changes state. This analysis will be very useful especially if the circuit operation is faulty.

Of course, in certain cases, the logic level will be able to be checked with the help of a logic tester or a simple voltmeter. With a simple voltmeter, however, it will not be possible to check the time sequences of pulses or even the interdependence between different signals, because these can be detected only one at a time.

Instead, all the advantages listed above will be achievable with a logic analyzer, an instrument that optically displays on a screen the logical states present at a certain number of points, during a certain time interval. It will then be possible to observe exactly whether the wire X is at level logic level "1," when line V switches to logic level "O," and what happens to pin Z.

A program and a suitable interface will be described next, with which it will be possible to transform the C-64 into an eight-channel logic analyzer.

Eight simultaneous measurements

Figure 1 shows the block diagram of the logic analyzer. Through the user port, the eight measurement lines (channels 1-8) will be fed to the Commodore 64. An additional connection is provided for the trigger (start of detection). The computer reads the data for a given time interval and displays it as illustrated in the figure.

Figure 1: Block diagram of the logic analyzer
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Figure 1: Block diagram of the logic analyzer

The program flowchart is drawn in Figure 2.

The visualization of the measurements is done by using the high-resolution graphic mode of the Commodore 64. For this purpose, this function will first have to be activated and image and color memories set up. Since the measurement can take place both with trigger and without, the trigger flag (measurement with trigger) is set as the initial value. After deleting any displayed image, depending on the status of the trigger flag, the measurement is triggered.

Figure 2: Flowchart
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Figure 2: Flowchart

A total of 256 values are measured and stored successively. For each measurement value (byte), a channel is associated with each bit. For example, if bit 0 is set, it means that in this measurement channel 1 is at logic level "1." If in the next measurement bit 0 is at logical "0," it means that the level of channel 1 has changed.

This data is now displayed on the screen, one channel below the other, as a plot against time. The image is stored and then can be observed at leisure.

Now you are faced with the following choice: a new measurement can be started with the trigger (F1) or without (F3). It is also possible to vary the measurement scale, which in the normal case is 1 ms per division, corresponding to about 5 ms per image. In this way even longer time intervals can be focused on the screen. The shortest displayable interval is about 50 microseconds and therefore signals at the high maximum clock frequency of 10 kHz can be measured.

Let us now see how the time diagrams are displayed on the screen.

Figure 3 shows the flowchart of this part of the program, which is in lines 470 to 500. The individual bits related to a channel are transferred one after the other in the carryover flag (shift to the right). Depending on the logic level of the carry flag (carry at logic "0" or "1"), the value to be displayed, which is in the Y register, is either incremented by 8 (equivalent to logic "1") or not incremented (equivalent to logic "0").

Figure 3: Flowchart of the program part required to display the image.
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Figure 3: Flowchart of the program part required to display the image.

The base values of the displayed diagram (zero lines of a channel) are each increased by 16, so the 8 time diagrams can be displayed one above the other.

The circuit is very easy

The interface schematic is shown in Figure 4. Values obtained from the measurement (channels 1-8) are applied to the data inputs (PB0-PB7) via eight NOR ports, which serve to protect the user port. The program is designed so that inverted data from the logic ports are displayed correctly.

Figure 4: Interface circuit
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Figure 4: Interface circuit

The trigger signal is applied, via TI, to the FLAG2 terminal of the user port. If a positive pulse arrives at the base of the transistor, FLAG 2 is raised to logic level "0."

Figure 5: Logical measurement experiment
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Figure 5: Logical measurement experiment

The flag bit in the interrupt request register is set, and then an interrupt is not performed and we simply stand by waiting for the start of the measurement (trigger action). The register will be polled, in a loop, as long as the flag bit remains set, then the measurement begins.

Figure 6: The data entered into the computer are displayed on the screen in the form of diagrams wit
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Figure 6: The data entered into the computer are displayed on the screen in the form of diagrams with respect to time

The trigger input can be shifted, so it is possible to choose which channel (signal) the oscillogram should start from. The trigger can also be activated from the outside, for example by a pushbutton. The circuit receives its supply voltage from the C-64, so no other power supply is needed.

Figure 7: Interface of logic analyzer with printed circuit boards
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Figure 7: Interface of logic analyzer with printed circuit boards

The program, in machine language, is loaded from the floppy disk into the C-64, with the command LOAD "LOGICK",8,1.

Figure 8: Printed circuit board and component layout
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Figure 8: Printed circuit board and component layout

The program will be started with SYS 49152, after which the measurement will begin immediately. If no signal is applied to the input, the screen will remain blank until a trigger pulse arrives. The measurement data must have TTL level. The program is interrupted with RUN/STOP and RESTORE.

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