The Model 323 Issue 2 All-Rate DSO-DP
The Conklin Instrument Corp. Model 323 Issue 2 All-Rate Digital Signal Zero Dataport (DSO-DP) with Secondary Channel is designed for use in the Digital Data System (DDS) network and in "DDS like" networks. This unit is designed to be installed in an AT&T Technologies D4 channel bank or SLC -96 subscriber loop carrier system shelf replacing the usual analog channel unit. Use of the unit provides a method of extending DDS service to a customer location from any serving central office having D4 channel banks or SLC-96 carrier systems connected via T-carrier facilities toward a DDS Hub Office.
The Model 323 All-Rate DSO-DP provides the interface between the 1.544 Mb/s bit stream of the D4 or SLC-96 terminal common equipment and the DDS DSO 64 kb/s bipolar signal. The DSO signal may then be cross-connected to multiplex equipment in a DDS Serving Office or connected in a tandem arrangement to another D4/SLC-96 channel bank in a DDS Tandem Facility Office if company policies permit. The Mode 323 supports all standard DDS data rates (2.4, 4.8, 9.6, 19.2, 56 and 64 kb/s) and also supports Secondary Channel operation (except at 64kb/s). Other features include optional Zero Code Suppression, Error Correction, and choice of Latching and/or standard OCU (HL96NY) Loopback. The Conklin Model 323 All-Rate DSO-DP may be used as a direct replacement for any AT&T compatible DSO-DP unit.
The Model 323 is electrically and mechanically compatible with D4 and SLC-96 channel bank shelves without modification of equipment or existing office wiring. DDS timing is provided by the office composite clock via the OIU-2 optioned for external timing. The front panel of the unit has LED status indicators and test jacks permitting evaluation and testing of the dataport circuit. Power requirements are minimal permitting maximum utilization of the D4 or SLC-96 channel bank shelf assembly.
FUNCTIONAL DESCRIPTION
Dataports allow DDS service, or similar digital services, to be extended to customers that cannot easily or economically be connected directly to a DDS End Office. The Conklin Model 323 DSO-DP permits the use of D4 and SLC-96 channel banks to provide DDS type service. Figure 2 shows a typical DDS Dataport application utilizing the Model 323 DSO-DP at a DDS Hub Office and any one of the companion Models from the Conklin Model 322 Series OCU-DP at the Serving End Office, often called a Dataport End Office. Figure 3 shows a Tandem Office application used to extend DDS service to the Serving End Office. Both are typical applications and illustrate the use of the Conklin Model 323 DSO-DP and Conklin Model 322 Series OCU-DP modules installed in a D4 or SLC-96 channel bank.
Figure 2- Typical DDS Dataport Application
================== =========================================
! ! ! !
! ___________ ! ! ____________ ____________ !
! ! ! ! ! ! ! ! ! !
! ! ! ! ! ! |--------! DSO ! ! ! DSO
! !______ ! ! ! ! | DSO !-----------! !----------->
! ! OCU |==========>LOCAL ! ! | DP !-----------! !<----------
! ! DP | ! ! LOOP ! ! |--------! 64Kb/s ! ! 64 Kb/s
! !_____|<=========== ! ! | !---- ----! !----------
! ! ! ! ! ! | !---- ----! !----------
! ! ! ! T-CARRIER ! ! |--------! ! ! !
! ! ! !===|\ /|=====! ! ! ! ! !
! ! D4 BANK ! ! |/ \| ! ! D4 BANK ! ! DSX ! !
! ! or ! ! 1.544 Mb/s ! ! or ! ! CROSS ! !
! ! SLC-96 ! ! ! ! SLC-96 ! ! CONNECT ! !
! ! RT ! ! ! ! ! ! ! !
! ! ! ! 2.4 ! ! ! ! ! !
! ! LOOP ! ! 4.8 ! !EXTERNALLY! ! ! !
! ! TIMED ! ! 9.6 ! ! TIMED ! ! ! !
! ! ! ! 19.2 ! ! ! ! ! !
! ! ! ! 56 ! ! ! ! ! !
! ! ! ! 64 Kb/s ! ! !<-------- ! ! !
! ! ! ! ! ! ! COMPOSITE ! ! !
! ! ! ! ! ! ! CLOCK ! ! !
! !---------! ! ! !----------! !----------! !
! ! ! !
! ! ! !
!================! !=======================================!
DDS END DDS HUB
OFFICE OFFICEThe customer's DDS 4-wire metallic loop directly interfaces any one of the Conklin Model 322 Series OCU-DP modules installed in a D4 or SLC-96 channel bank located near the customer. Customer data is converted to a 64 kb/s digital signal which interfaces the D4 or SLC-96 terminal common circuitry. This signal occupies a single time slot of the 1.544 Mb/s DS-1 bit stream. Two time slots are required for 56 or 64 kb/s circuits employing error correction.
The data rate in the figure above is 1.544 Mb/s. This data rate is designated DS-1 and is subdivided into 24 channels of 64 kb/s data, designated DS-0. The Serving End Office is connected to a Tandem Office or directly to a DDS Hub Office by a T-carrier facility.
The Model 323 DSO-DP is designed to be installed in a D4 or SLC-96 shelf located at a DDS End Intermediate, or Hub Office. The unit electrically interfaces the common circuitry of the shelf. Transmission of customer data occupies a single time slot of the DS-1 signal transmitted via a T-carrier system. This data is converted by the Model 323 to a DSO-A bipolar 64 kb/s signal for cross-connection to another D4 or SLC-96 channel bank, or to T1 Multiplex equipment for transmission toward the DDS Hub Office. The unit also performs the reverse function.
The Model 323 DSO-DP is designed to provide a choice of loopback and test access options. There are three products in this family:List 1,List 2, and List 4. The Model 323 List 1 and List 4 units are designed to detect and respond to either the standard DDS-OCU Loopback (HL96NY) or Latching Loopback. The Model 323 List 2 unit is designed to detect and respond to only the standard DDS-OCU Loopback (HL96NY) Tables A and B show the OCU (HL96NY) Loopback and Latching Loopback codes sequences respectively. The loopback code sequences may be transmitted from the DS-O or DS-1 directions. Loopback commands detected from the DS-O side will implement a DS-1 Loopback and commands detected from the DS-1 direction will implement a DS-O Loopback. The List 1 unit may be optioned to a permit either or both loopback types to be enabled or disabled. The List 4 units have a special front panel test access configuration that reverses the Near/Far logic test direction from that of the List 1 unit. In all other respects, the List 1 and List 4 units are identical.
Detection of the Latching Loopback code sequence will place the List 1 or List 4 units in a latched loopback mode which will remain in effect for the List 1 and List 4 units until the correct loopback release code has been detected. Front panel LEDs "TEST" and either "DSO LB" or "DS1 LB" will be illuminated to indicate the loopback point. Latching Loopback differs from the standard DDS- OCU Loopback in that restrictions on the type of data transmitted are eliminated.
Detection of standard OCU Loopback code will implement the HL96NY Loopback and illuminate the front panel LEDs "TEST" and either "DSO LB" or "DS1 LB" to indicate the loopback point. Once looped, detection of a short burst of all ones will release the loopback at the DSO-DP and cause the downstream dataport to enter loopback. The downstream dataport may be another DSO-DP in a tandem configuration or an OCU-DP. The front panel LED "TEST" will remain ON when the loopback is at a downstream dataport. All other front panel LEDs will be OFF. Thus, the loopback point may be electronically "stepped" from the Loop- Side Interface module (Conklin Models HL96NY and 222), to each Conklin Model 323 DSO-DP, and finally, to the OCU-DP. Removal of the OCU Loopback code from the data stream will release all loopbacks and return all dataports to the normal operating mode. The OCU Loopback option must be turned OFF for 64 kb/s Clear Channel circuits.
Additional operating features of the Model 323 All-Rate DSO-DP include Secondary Channel Capability, Error Correction and Zero Code Suppression. Front panel LEDs provide a visual indication of loopback status and an idle circuit condition. The following panel indicators are provided:
- TEST (Green LED)
- DSO LB (Loopback) (Green LED)
- DS1 LB (Loopback) (Green LED)
- IDLE CKT (Yellow LED)
TABLE A. OCU LOOPBACK CODE SEQUENCE (FOR LIST 1, LIST 2, AND LIST 4 UNITS)
___________________________________________________________________________
| | | |
| SEQUENCE | CODE TRANSMITTED | RESPONSE |
|_________________|___________________|_____________________________________|
| | | |
| 1. Data (normal | SDDDDDD1 (Data) | Data to Customer. |
| | | |
| 2. Initiate OCU | S0101010/SDDDDDD1 | LSI (CIC Model HL96NY) Looped. |
| Loopback | | |
| | | Verify Error-Free Data. |
| | | |
| 3. Send Burst | S0101010/S1111111 | LSI Loopback Released. |
| of All 1's | | |
| | | DSO-DP (CIC Model 323) Looped. |
| | | |
| 4. Send Burst | S0101010/S1111111 | DSO-DP (CIC Model 323) Loopback |
| of All 1's | | Released. |
| | | |
| | | OCU-DP Looped. |
| | | |
| | | Verify Error-Free Data. |
| | | |
| 5. End OCU | SDDDDDD1 | All Loopbacks Released. |
| Loopback | | |
| | | Data to Customer |
|_________________|___________________|_____________________________________|- The symbol "S" represents the appropriate sub-rate framing bit for sub- rate service and the least significant data bit for 56 kb/s service. This bit can be either 0 or 1 for the above codes. The symbol "D" represents random data and can be either 0 or 1.
- The use of the "/" separating the two codes indicates an alternating Loopback code/Data pattern as generated by existing portable DDS test equipment.
- When DSO-DP's are connected in a tandem configuration, the second burst of all 1's will loop the second DSO-DP downstream of the LSI, the third burst of all 1's will loop the third DSO-DP, and so forth until the loopback occurs at the OCU-DP. At this point, subsequent transmission of all 1's will not affect the loopback at the OCU-DP.
TABLE B. LATCHING LOOPBACK SEQUENCE (NOT APPLICABLE TO LIST 2 UNITS)
____________________________________________________________________________
| | | |
| SEQUENCE | CODE TRANSMITTED | RESPONSE |
|_________________________|___________________|____________________________|
| | | |
| 1. Data (normal) | SDDDDDD1 (Data) | Data to Customer. |
| | | |
| 2. Transition in | S0111010 (TIP) | Clear all Loopbacks. |
| Progress | | |
| | | |
| 3. Loopback Select Code | S0000101 (LSC) | Direct Loopback to DSO-DP. |
| (Unique for DSO-DP) | | |
| | | |
| 4. Loopback Enable | S1010110 (LBE) | After 30 Bytes send MAP |
| | | code Downstream. |
| | | |
| 5. All-Ones Bytes plus | S111111/S1010110 | Activate Selected DSO-DP |
| Loopback Enable | | for Loopback |
| | | |
| 6. Far End Voice | S1011010 (FEV) | Activate selected Loopback.|
| | | |
| 7. Data Test Mode | SDDDDDDD (Data) | Verify Error-Free data. |
| | | |
| 8. Exit Loopback Mode | S0111010 (TIP) | Clear all Loopbacks |
| | | |
| 9. Data (Normal) | SDDDDDD1 (Data) | Data to Customer. |
| | | |
|_________________________|___________________|____________________________|- The symbol "S" represents the appropriate sub-rate framing bit for sub- rate service and the least significant data bit for 56 kb/s service. This bit can be either 0 or 1 for the above codes. The symbol "D" represents random data and can be either 0 or 1.
- Sequence number 5 in the above table is used only when multiple DSO- DP's exist in a tandem configuration. In this case, sequence 5 should be executed (N-1) repetitions where N is the number of DSO-DP's that lie between the test center and the desired loopback point. This step should not be executed for circuits with only one DSO-DP.
- After 30 or more LBE Bytes are received, any code can be interleaved between the remaining LBE and FEV Bytes to complete the Latching Loopback sequence. Therefore, at least 30 Bytes of TIP should precede and follow all procedures to clear all modules within a system configuration.
- The Latching Loopback of the Model 323 Issue 2 List 1 and List 4 units do not have a time-out feature. Once it is activated, it will stay activated until the proper clear code is received.
Test access is provided by bantam jacks on the front panel. These jacks permit test signals to be transmitted to, and received from, the DSO-0 or the DS-1 directions and may also be used to implement a manual loopback with a bantam-to-bantam patch cord.
The Conklin Model 323 DSO-DP supports all error correction modes compatible with existing dataport sub-rate 56 and 64 kb/s data requirements. Option switches are provided permitting error correction configurations that are compatible with D4 and SLC-96 operating modes.
Zero code suppression, normally enabled, may be optionally disabled allowing unrestricted 56 kb/s Secondary Channel data and 64 kb/s Clear Channel data to be transmitted over T-carrier facilities.
CIRCUIT DESCRIPTION
The following circuit description helps to emphasize the overall performance of the DSO-DP Unit.
COMMON CIRCUITS
The Model 323 DSO-DP, when installed in a D4 or SLC-96 channel bank shelf, will interface the common circuitry associated with the channel banks. The interface provides access to the DS-1 PCM Bus, the integrated 64/8kHz Clock, Channel Select Timing signals, and the Out-of-Frame signal.
All interface signals are provided at the card-edge connector of the Model 323 DSO-DP. Modification of the D4 or SLC-96 channel bank shelf is not required.
CLOCK BUFFER
This circuit is common to all other circuits of the DSO-DP and generates all timing signals required for rate matching and synchronizing customer data to the DDS Reference Clock. These timing signals are derived from the office scomposite clock supplied to the common circuitry of the D4 or SLC-96 channel bank.
ERROR CORRECTION CIRCUITS
Use of dataports to provide DDS service over T-carrier systems used primarily for analog service may require the use of error correction techniques to meet established DDS error rate performance objectives. Two error correction techniques are utilized in the Model 323 All-Rate DSO-DP module. A repeat-of-five majority-voting scheme is used for DDS sub-rate service and takes advantage of the redundancy of the sub-rate data. For 19.2 and 56/64 kb/s data rates, a shortened Golay code is used to generate a parity byte which is transmitted along with the data byte. Error correction at 56/64 kb/s requires two 64 kb/s data channels occupying two of the DS-1 time slots, one for customer data and the other for the parity bit stream generated by the Error Correction Encoder.
DDS NETWORK TO T1 FACILITY PATH
BIPOLAR TERMINATOR
The DDS 64 kb/s balanced bipolar digital signal from the DDS network, via the DSX-0A level cross-connect, is transformer-coupled to the input of the Bipolar Terminator. This circuit converts the bipolar input signal to a logic level signal for interface to the Loopback Code Detection circuit.
LOOPBACK CODE DETECTOR
This circuit will detect loopback codes received from the DS-0 direction, usually transmitted from the STC. A loopback option switch may be set to enable or disable either the standard OCU Loopback or Latching Loopback on the List 1 and List 4 units; or only the standard OCU loopback on list 2 units. The circuit is transparent to all other loopback codes.
Detection of the appropriate loopback code sequence received from the DS-0 direction will implement a logic level loopback at a point internal to the unit. Front panel indicators "TEST" and "DS1 LB" are controlled by this circuit and will be illuminated when this loopback is in effect.
ZERO CODE SUPPRESSION
This circuit block monitors data transmitted from the DDS network toward the T1 facility. The circuit will substitute the Unassigned MUX Channel (UMC) code for a byte of data containing all 0's
An option switch permits the Zero Code Suppression function to be disabled. Normally, this option should be enabled. Disabling of Zero Code Suppression allows for unrestricted transmission of 56 kb/s secondary channel data into the T1 facility when B8ZS encoding becomes available for D4. Zero Code Suppression should also be disabled for 64 kb/s Clear Channel operation.
ERROR CORRECTION ENCODER
The Error Correction Encoder circuit monitors data transmitted toward the T1 facility and will implement the appropriate correction scheme based on the data speed and the setting of the Error Correction option switch. This switch selects sub-rate 19.2 or 56/64 kb/s Error Correction. Several 56/64 kb/s error correction modes are provided to maintain compatibility with both D4 and SLC-96 channel bank operating modes. Error Correction may also be disabled.
TRANSMIT RATE CONVERTER
This circuit converts the DDS 64 kb/s byte-encoded signal to the format required for interface to the PCM Bus and D4 or SLC-96 common circuitry. Clocking of the data is controlled by the channel bank common circuitry. The data is clocked into the proper time slot of the DS-1 bit stream. Clock signals from the Clock Buffer retime and synchronize the data to the DDS Bit Clock.
The output signal from this circuit connects to the Tri-State Buffer which interfaces the DS-1 PCM Bus associated with the common circuitry of the D4 or SLC-96 channel bank.
T1 FACILITY TO DDS NETWORK PATH
RECEIVE RATE CONVERTER
Byte-encoded 64 kb/s data received during a single DS-1 time slot is gated to the input of this circuit by Channel Select timing signals. The circuit converts the data to a 64 kb/s DS-0 logic level signal.
ERROR CORRECTION DECODER
This circuit monitors data received over the T1 facility. The circuitry detects and corrects bit errors by application of the appropriate error correction scheme for the data rate in use. The error correction function is configured for sub-rates 19.2 or 56/64 kb/s by the option switches.
OUT-OF-SYNC CODE INSERTION
Failure of the T-carrier span line or the D4/SLC-96 channel bank will activate the Out-of-Frame alarm associated with the channel bank common circuitry. This alarm signal interfaces the Out-of-Sync Code Insertion circuit which will generate and insert in the data bit stream the Out-of-Sync Code for transmission toward the DS-0 direction.
LOOPBACK CODE DETECTION
This circuit will detect loopback codes received from the DS-1 direction. The circuit operates in the same way as the Loopback Code Detector discussed previously. Loopback option switches may be set to enable or disable either the standard OCU Loopback or the Latching Loopback as discussed earlier. The circuit is transparent to all other loopback codes.
Detection of the appropriate loopback code sequence received from the DS-1 direction will implement a logic level loopback at a point internal to the unit. Front panel indicators "TEST" and "DSO LB" are controlled by this circuit and will be illuminated when this loopback is in effect.
BIPOLAR DRIVER
The 64 kb/s byte-encoded data signal received from the T1 facility for transmission toward the DDS network interfaces the Bipolar Driver circuit and is converted to a DS-0 64 kb/s balanced bipolar signal which is transformer- coupled to the DSX-0A cross-connect point.
Well there ya have it, An inside look at some of the digital equipment that operates in your local CO. I hope this file has been helpful or insightful to any of you that found it interesting.
