Beyond 512 kb: The Two Megabyte REU
By Andrew E. Mileski
Copyright October 3, 1989.
In Volume 9, Issue 6 of the Transactor, Paul Bosacki showed us a miracle; the one megabyte C64. Paul had developed an elegant method of allowing the C64 to access this extra memory out of the C64's own memory map. Unfortunately, this extra RAM is rather difficult to access, not all of it is available to the user, and C128 owners cannot expand there machines in the same manner. The circuit necessary for this feat allows a C64 to use 256 k RAM chips, instead of the 64 k RAM chips it was designed to use. Although a brilliantly simple circuit, it is over-kill when one already has a Ram Expansion Unit (REU) that directly supports 256 k RAM chips!
Expanding a REU is relatively simple, and if you already know how to program a REU you can easily take advantage of an expanded one. In fact, all your software that uses a REU is completely compatible! Now are fellow C128 owners can expand their machines easily too, since the extra RAM is accessed out of a REU, and not off a modified mother-board!
In a 512 kb REU, there are two dynamic RAM chip banks on the circuit board. They each consist of eight, 1 bit by 256 k dynamic RAM chips, which gives us our 512 k bytes. The REU's internal bank register at $DF06 works in 64 kb increments, and has only eight of these REU banks. Banks 0 to 3 are accessed out of chip bank one (U2 to U9), and banks 4 to 7 are accessed out of chip bank two (U10 to U17). Please note the distinction between chip banks, and REU banks.
Note: signals proceeded by an asterisk indicate that they are active low
Dynamic RAM Basics
Dynamic RAM memory chips are constructed with multiplexed address inputs. This means that they carry different information at different times. To access a particular memory cell, we first supply the chip with half of the actual address, a row address. Next we latch this address into the chip by asserting the Row Address Strobe (*RAS). Now we supply the chip with the other half of the address, the column address. Once again we latch this address into the chip by asserting the Column Address Strobe (*CAS). Depending on the state of the Write Enable (*WE) signal, a read or write memory cycle will occur.
Unfortunately dynamic RAMs forget everything unless they are reminded, or refreshed. This must be done about every 4 milliseconds! To refresh the memory a RAS only cycle must be done for every row address. This means that only the row address is latched into the chip; the column address is not needed here. The entire row of data stored in the chip will be refreshed, and our data will be safe for another few milliseconds. In a REU the RAM Expansion Controller (REC) chip takes care of all this for us.
Fooling the REC
Since a REU was only designed to access 512 kb of expansion memory, we must fool it in order to access more. We do this by letting the REU think that it has only 512 kb available at any one time. This means we need some way to switch between the extra banks of memory. The circuit shown in the schematic helps us to do this by adding two bits to the REU bank select register. This two bit output port lets us select one of four banks of 512 kb. So in other words, are REU now thinks it is four separate 512 kb REUs. Now we can easily access up to 2 Mb out of a REU!
How the circuit works
The secret to expanding dynamic memory lies in the *CAS signal. Since all the RAM chips need to be refreshed with *RAS, we don't do anything to this signal and pass it to all memory chips. This leaves us with manipulating *CAS.
Manipulation of *CAS is the job of IC1, a dual two to four line decoder/demultiplexor. It is used to direct the REC signals *CAS0 (chip bank one), and *CAS1 (chip bank two), to the correct bank of eight RAM chips. When one of the REC CAS signals is asserted, the CAS signal of the selected bank is asserted. The bank selection is done with the two select inputs S0 and S1 of IC1.
IC2 and IC3 form a two bit write-only register, whose outputs are the bank select inputs to IC1. Bits 3 and 4 of the REU bank register at $DF06 are latched into IC2, two D type flip-flops, on the negative edge of the system clock (theta2). By mapping our new two bit register to these normally unused bits, the extra memory appears to the user as extra 64k banks beyond the normal maximum of 512 kb. IC3 is a 3 to 8 line decoder/demultiplexor, which is used to decode the lowest three bits of the I/O2 page ($DF00 to $DFFF) address. The IC3 signal *O6 is used as the clock signal for the two flip-flops, which latches bits 3 and 4 of the data bus on the positive edge. This happens whenever $DF06 is written to. On a read memory cycle to $DF06, IC3 is disabled and the REU's regular internal register appears on the data bus.
A switch pulls the *CLR inputs to each of the flip-flops low when it is closed (position 1). This forces them to select bank zero of 512 kb at all times, which is present in all 512kb REUs. When the switch is open (position 2), the flip-flops can freely take on the values of bits 3 and 4 of $DF06. This allows complete software compatibility with a 1750 (512 kb) REU.
Lastly, the two Light Emitting Diodes (LEDs), which are optional, simply show us (in binary) what bank of 512k we are using. They allow us to quickly check software compatibility, as explained later.
Installation
All the expansion hardware fits inside the REU case. You will not be able to use the RF shield, and it will be a very tight fit with all 2 Mb installed (don't use IC sockets!). Start by expanding your REU to 512 kb, or in other words you need a 1750 REU. See Volume 9, Issue 5 of the Transactor, or the article by ScottB30 on Quantum Link for expanding 1764 and 1700 REUs. Take the usual static precautions, and of course, any modification to the REU will void the warranty! Proceed at your sole risk!
On the component side of the REU, with the edge connector towards you, locate Resistor Package RP3 on the left side near the middle of the board. Flip the board over to the solder side, again with the edge connector towards you. Locate RP3 again on the right side of the board. From the top of the board, find pin 7 of RP3 and cut the trace leading away from the pin. Solder a wire to this pin (pin 7); this is the *CAS0 signal. Find pin 3 of RP3 and again cut the trace leading away from the pin. Solder a wire to this pin (pin 3); this is the *CAS1 signal.
Flip the board over to the component side with the edge connector towards you, and locate ram chips U2 and U10 on the top left side of the board. Flip the board over to the solder side and again locate these chips. To pin 15 of U2 solder a wire; this is the *CASBANK0 signal. Solder a wire to pin 15 of U10; this is the *CASBANK1 signal. Run the four wires you now have, down to the right side of the edge connector and secure them in the corner with a piece of electrical tape. This completes all the solder connections to the solder side of the board.
Locate the fifth pin from the right on the edge connector and follow the trace to a component leg; note the placement. Flip the board to the component side for the last time, and locate the component. It is labeled FB2, and should be a Ferrite Button, but is a 430 Ohm resistor (yellow, orange, brown, gold bands) on my REU. To the opposite end of the component, away from the edge connector, solder a wire; this is the system clock signal theta2.
Locate the thirteenth pin from the right on the edge connector. Follow the trace to a pass-through, and solder a wire into it; this is the *I/O2 signal.
Locate the eighteenth pin from the right of the edge connector, and follow the trace to Ferrite Button FB1. To the side away from the edge connector solder a wire; this is the R/*W signal.
Locate the empty pinout (U18) next to the square REC chip. Solder wires into the holes for pins 8, 9, 10, 14, 15, 16, and 28. These are the signals A2, A1, A0, Ground, D3, D4, and +5 volts respectively. This completes the signal hunting.
Lay a 2 inch strip of double-sided foam tape down the center of the missing IC (U18) pattern. Try to leave room near the right edge of the case so you can mount a switch. Mount the ICs, in order from left to right, to the tape UPSIDE DOWN (pins sticking up) with the notches (or dots) towards the top of the board. Place them as far apart as you can on the tape.
Now connect the ICs using (carefully!) point to point soldering, or wire-wrap DIRECTLY on the IC pins (yes, it can be done). If you do wire-wrap, only 4 wraps per connection are necessary, and "over wrapping" (wrapping on top of wrapping) is recommended for the second connection to a pin. Keep the connections as short as possible eg. +5 volts to pin 14 of IC1 in mine is 1/4 of an inch long.
Mount the switch in the top half and on the edge of the REU's case in a convenient place. I recommend placing it near the bottom right corner, near the plastic post since there is nothing in the way here. A slide switch is neater than a toggle switch, but it isn't very much fun trying to make a square hole for a the slide switch! Mark (or just note) the position of the switch on the case (open: 2 Mb, closed: 512 kb) with a marker (Sanford "Sharpie" writes permanently on anything!) or use "Lettra Set" type lettering.
The next step, and last step, is to wire and mount the two optional LED indicators. Solder wires to all the leads of both the LEDs. Drill holes for them at the top edge, of the top half of the case, so they're visible with the REU installed. Make sure to put LED1 on the left and LED0 on the right, so you can read the bank of 512 kb in binary (0=un-lighted, 1=lighted).
Your REU now works the same as before, at least it should! Plug it in, move the switch to position 1 (switch closed, the optional LEDs should both be un-lighted) and give the REU a spin with any test program of your choice. If things look bad, power down and recheck all connections! If it does work, congratulations! You now have an REU that can be expanded to 2 Mb by adding a meager (48) RAM chips.
Adding memory
Expand the memory by piggy-backing the existing RAM chips in chip banks one or two, starting with chip bank 1. Bend pin 15 up, to a 45 degree angle, on each of the RAM chips to be added. Connect a wire to this pin before soldering it to the other RAM chip. Once the chip is soldered in place, connect the wire to pin 15 of the next RAM chip to be added. Solder another wire to its pin 15, and solder the chip in place next to the other. Continue in this way until all the RAMs in a chip bank are piggy-backed, and all pins 15 are connected in a daisy-chain fashion in each chip bank. Solder a wire to pin 15 of the rightmost RAM chip in the bank; this is the *CASBANKx signal. Now use an ohmmeter or continuity tester to see that all the chips in the newly added bank share the same signals on pins 1, 3 to 13, and 15 and 16.
All that is left is to connect the wire *CASBANKx to an appropriate numbered signal on IC1. Odd numbered CASBANK signals are for RAM chips piggy-backed in chip bank one, even numbered ones are for RAM chips piggy-backed in chip bank two. Choose the next available signal when adding a new bank of RAMs. *CASBANK0 and *CASBANK1 are reserved for the two chip banks already in a 512 kb REU. Connect the *CASBANKx signal, and you now have another 256 kb of memory! Repeat for chip bank two for 512 kb extra RAM. Add just as much RAM as you need in 256 kb increments!
Programming an expanded REU
You don't need to do anything different to use the extra memory in the REU. Just remember that you now have more 64 kb banks that you can access through the bank register at $DF06 when in 2 Mb mode (switch in position 2). When in the 1750 emulation (512 kb) mode (switch in position 1), remember you only have access to banks 0 to 7 of 64 kb. Keep in mind the peculiarities of the 2 Mb mode as well. That's all there is to it! The number of banks depends on how much memory you added; 0 to 15 with 1 Mb, and 0 to 31 with 2 Mb for example.
Note that all software that tests for a REU will only find 512 kb available, so a slightly different memory test is necessary to check on how much expansion memory we have. Since the REU can be expanded up to 2 Mb in 256 kb increments at the users discretion, a slightly different test is mandatory to figure out just how big the REU is. See listing 1 for an example.
Peculiarities
There are a few very minor inconveniences with this expansion project detailed as follows:
- The REU will not wrap internally between banks of 512 kb, instead the REU will wrap to the beginning of the same 512k bank. For example, saving 2 bytes to $FFFF in bank 7 will put one byte at $FFFF in bank 7, and the other at $0000 in bank 0 NOT bank 8 as expected. This is because the REC chip does not recognize more than 512 kb directly; we have fooled it to use more RAM.
- Bank register at $DF06 is write-only where bits 3 and 4 are concerned. If $DF06 is read, bits 3 and 4 (as well as bits 5, 6, and 7) will always be one no matter what bank of 512 kb the REU is in.
- Bits 3 and 4 of the bank register at $DF06 are now significant, but in an unexpanded REU they are ignored. This why we have a switch to disable all but 512k of memory when we run into non-compatible software. See the next section for details.
- The 512 kb bank select bits are memory mapped by only the three lowest address bits. This means there are images of these bits at $DF0E, $DF16, $DF1E, etc. This is a trivial matter since no sane person uses image addresses!
Compatibility
There is only one source of software incompatibility in this modification; the 2 bit 512 kb bank select register we had added to $DF06. Since these two bits are now significant and didn't used to be, we could have a problem; software that doesn't set these bits to the same value at all times, or sets the bits to a bank of 512 kb that isn't installed yet, won't work. But this is what the switch is for!
The 2 Mb modification is 100% compatible with any software written for a 1750 (512kb) REU, when in the switch selectable 1750 emulation mode (position 1, switch closed). Unfortunately none of the extra memory beyond this can be accessed when in this mode. This is of no consequence, since the software can't make use of any additional memory anyway.
When the 2 Mb mode is switch selected (position 2, switch open), we have complete access to how ever much memory we have added. The switch should be in position 2 whenever possible! Most software can function in this mode, including GEOS!
The two optional LEDs are very useful to determine if the software is compatible in the 2 Mb mode. If you are using software meant to be used with a 1750 REU, you can use the software in the 2 Mb mode if: during a REU transfer the LEDs are always showing the same bank of 512 kb is being accessed (LEDs not flickering), and they indicate a bank that is installed (bank 0 of 512 kb is always present). Without the LEDs, it is simply a matter of saying "It works", or "It doesn't work" when you use software for a 1750 REU.
Final words
Don't let the length of this article discourage you; it only seems difficult in print! Your REU can now contain more memory than an average IBM PC. So be nice to your IBM buddies, and don't brag too much! I can be reached on Q-link (screen name Recursion), or you can write me directly if you have any questions, comments, or construction ideas.
Andrew E. Mileski
210-180 Lees Avenue
Ottawa, Ontario
Canada, K1S 5J6
Listing 1: Recommended type of REU memory check
It is implemented here in BASIC with a REU wedge for the C64, but can easily be translated into assembly. This check will always return the number of 64 k byte banks that are useable in the REU. FETCH and STASH do exactly what you might think. The operands are bytes to transfer, computer base address, REU base address, and REU bank (of 64 kb) number.
2000 REM ****INITIALIZE ****
2010 REM Put a single status byte, that shows an unchecked bank, in each bank
of 64kb.
2020 POKE 49152,136
2030 FOR I=0 TO 255
2040 !STASH 1,49152,0,I
2050 NEXT
2060 REM **** TEST ****
2070 REM Test for # banks present by seeing if bank checked yet. If not, change status of
2080 REM bank to checked, and add 1 to the # of banks. Else, bank is checked already and
2090 REM we're done! Note that we only test one byte per bank to speed things up.
2100 POKE 49152,27
2110 I=0
2120 !FETCH 1,49152,0,I
2130 IF PEEK(49152)<>136 THEN 2190
2140 POKE 49152,27
2150 !STASH 1,49152,0,I
2160 I=I+1:IF I<256 THEN 2120
2170 REM **** DONE ****
2180 REM Number of banks of 64kb is now in I.
2190 IF I=0 THEN PRINT "REU NOT PRESENT, OR NOT SEATED PROPERLY"
2200 IF I=2 THEN PRINT "THIS IS A 1700 (128 K) REU"
2210 IF I=4 THEN PRINT "THIS IS A 1764 (256 K) REU"
2220 IF I=8 THEN PRINT "THIS IS A 1750 (512 K) REU"
2230 IF I>8 THEN PRINT "THIS IS AN EXPANDED"; 64*I ;"K REU"
Parts List and Miscellaneous Data
Required parts
- IC1: 74F139 (Dual 2 to 4 line decoder/demultiplexor.)
- IC2: 74F74 (Dual D-type flip-flops.)
- IC3: 74F138 (3 to 8 line decoder/demultiplexor.)
FAST series components recommended!
- 3.3k Ohm Resistor, 1/4 watt and 5% tolerance.
- SPST micro-mini toggle, or slide switch.
- Two inch strip of double-sided foam tape.
- Supply of 30 gauge wire.
- And other standard tools and equipment.
Optional
- Two LEDs T-1 size.
- Two 390 Ohm resistors, 1/4 watt and 5% tolerance.
Pin connections
IC1
Pin 16: +5 Volts 1: *CAS0
15: *CAS1 2: IC2 pin 5
14: IC1 pin 2 3: IC2 pin 9
13: IC1 pin 3 4: *CASBANK0
12: *CASBANK1 5: *CASBANK2
11: *CASBANK3 6: *CASBANK4
10: *CASBANK5 7: *CASBANK6
9: *CASBANK7 8: Ground
IC2
Pin 14: +5 Volts 1: **1**
13: **1** 2: D3
12: D4 3: IC3 pin 9
11: IC2 pin 3 4: +5 Volts
10: +5 Volts 5: IC1 pins 2,14
9: IC1 pins 3,13 6: LED0 **2**
8: LED1 **2** 7: Ground
IC3
Pin 16: +5 Volts 1: A0
15: No connection 2: A1
14: No connection 3: A2
13: No connection 4: *I/O
12: No connection 5: R/*W
11: No connection 6: Theta2
10: No connection 7: No connection
9: IC2 pins 3,11 8: Ground- Connect this pin to one side of the switch. There should be two pins connected to the same side of the switch. To the same side of the switch connect a single 3.3k Ohm resistor. Connect the free end of the resistor to +5 Volts. Connect the other side of the switch to ground.
- Connect this pin to the cathode of the LED shown. Connect the anode of each LED to its own 390 Ohm resistor. Connect the free end of each resistor to +5 Volts.
Top of ICs are indicated by a dot or notch. When the chips are installed up-side-down, the pin numbering is clockwise from the top right pin! Since the RAM chips are installed right-side up, their pin numbering is counter clockwise from the top left pin. Don't mix up the numbering!!!
Note
This file was converted from the original geoWrite 2.1 file by the author. The schematic in geoPaint format has been reduced into the pin connection table shown above. If you have GEOS 2.0 I recommend you obtain the original ARCed files from Q-Link ("BEYOND512KB.SDA" by Recursion)
BEYOND512KB.SDA
