Building a DSP board, Part One: Choosing the DSP chip
This will be the first in a series on how I went about building a dual Motorola DSP56000 sampling board.
First, I needed a goal.
Goal: a DSP board that takes two channels of audio (a stereo pair) and produces up to four channels of output.
Why is this my goal? I want to do Dolby Surround (the right way!) and that requires four channels.
Now we need to decide which processor to build around. We'd need at least a 16 bit processor (want CD quality), but would like more bits to avoid round off errors. Also, I wanted something that would be easy to program and easy to interface. Looking around at the AES convention down in LA, I found that just about everyone there was using the Motorola 56000. It is a 24 bit processor (don't have to worry about round off error) and has a lot of stuff built right into the chip (8 bit host port, synchronous serial interface, and asynchronous serial interface). Also, being from Motorola, it had an assembly language that made sense to me (I love the 680xx series of microprocessors). I had previously used the Texas Instruments 32010, and did not like its assembly at all. I talked with the Motorola rep at the convention and saw a digital graphic equalizer that had hardly any support chips. I knew right then that the 56000 was the DSP chip I wanted.
[ Note: Some people might be getting confused between the 56000 and the 56001. The only difference is that the 56000 comes with your application and data already blown into its internal ROM. The 56001 has a bootstrap program that allows loading from either the host port or a cheap external ROM and a sine table and a-law/mu-law tables preblasted into ROM. So, when I say I'm using the 56000, I'm really using the 56001. You have to buy mega quantities to get your stuff preburned. ]
Here are some stats on the 56001:
- 512 words of program memory
- Two banks (X and Y) of data memory (ideal for stereo applications!)
- Data ROMS as mentioned above
- At 20.5 MHz, does 10.25 MIPS (1024-point complex FFT in 3.3 ms) (New 28 MHz version available now!)
- Data path is 24 bits wide and internal accumulators are 56 bits wide
- High degree of parallelism allows instruction prefetch, 24x24 bit multiply, 56 bit addition, two data moves, and two address pointer updates (using either linear, modulo, or reverse carry) to all be executed in *one* cycle!
- Has Serial Comm Interface, Synchronous Comm Interface, and 8 bit Host port
Next: I choose the DACs and ADCs!
