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STE Reference Documentation, v1.00 for ST User CoverDisk
Another STE extra from Adam Greenwood
The following list is a complete reference for the STE, including all new registers and variables plus original ones which are of special interest on the STE. This list is designed to be used in conjunction with the ' Inside the STE ' series of articles.
=================
1. DMA SOUND CHIP
=================
1.1 SOUND CHIP REGISTERS:
-------------------------
$ff8900 (r/w) enable register:
00 - disable sound (default state)
01 - enable sound, play once
11 - enable sound, loop forever
$ff8902 (r/w) frame base address high
$ff8904 (r/w) frame base addeess middle
$ff8906 (r/w) frame base address low
$ff8908 (ro) frame address counter high
$ff890a (ro) frame address counter middle
$ff890c (ro) frame address counter low
$ff890e (r/w) frame end address high
$ff8910 (r/w) frame end address middle
$ff8912 (r/w) frame end address low
$ff8920 (r/w) sound mode control:
bit 7 6 5 4 3 2 1
use m . . . . r r
m - 0 = stereo mode, 1 = mono mode
rr - 00 = 6.258 kHz frequency
01 = 12.517 kHz
10 = 25.033 kHz
11 = 50.066 kHz
1.2 INTERRUPT CONTROL:
----------------------
MFP Interrupt vectors for sound control:
$134 Timer A vector
$13c GPI(7) mono monitor detect vector
MC68901 MFP configuration registers for sound:
$fffa03 Active edge
$fffa07 Interrupt enable A
$fffa0f Interrupt in service A
$fffa13 Interrupt mask A
$fffa19 Timer A control
$fffa1f Timer A data
Timer A uses bit 5, GPI(7) bit 7
Shift mode register:
$ff8260 Shift mode
For interrupt at start of sample:
Screen mode Active edge
----------- -----------
2 (mono) Positive - or.b #$80 with edge
0,1 (colour) Negative - and.b #$7f with edge
1.3 VOLUME/TONE CONTROL:
------------------------
Microwire registers:
$ff8922 microwire data register
$ff8924 microwire mask register
Volume/Tone addresses and parameters:
Master Volume: 10 011 DDDDDD
Left Volume: 10 101 xDDDDD
Right Volume: 10 100 xDDDDD
Treble: 10 010 xxDDDD
Bass: 10 001 xxDDDD
Mix: 10 000 xxxxDD
Where x indicates don't care, and D is a data bit.
Volume/Tone data values:
Master Volume: 0 - 40 (0 = -80dB, 40 = 0dB)
Left/Right Volume: 0 - 20 (0 = -80dB, 20 = 0dB)
Treble/Bass: 0 - 12 (0 = -12dB, 6 = 0dB, 12 = +12dB)
Mix: 0 - 3 (0 = -12dB, 1 = Mix PSG, 2 = don't mix
PSG, 3 = reserved)
=====================
2. VIDEO SHIFTER CHIP
=====================
2.1 EXTENDED COLOUR PALETTE
---------------------------
$ff8240 - $ff835e rgb colour registers
colour word:
bit 11 10 9 8 7 6 5 4 3 2 1 0
meaning R0 R3 R2 R1 G0 G3 G2 G1 B0 B3 B2 B1
Rx = Red , Gx = Green, Bx = Blue
where x = bit no.
Giving the following colour range:
intensity level 0 1 2 3 4 5 6 7 8 9 a b c d e f
4-bit nibble 0 8 1 9 2 a 3 b 4 c 5 d 6 e 7 f
2.2 SCREEN ADDRESS REGISTERS
----------------------------
$ff8201 screen base address high (vbasehi)
$ff8203 screen base address middle (vbasemd)
$ff820d screen base address low (vbaselo)
2.3 HORIZONTAL SCROLLING
------------------------
$ff820f over-length line width (linewid)
$ff8265 pixel scroll offset (hscroll)
===============
3. BLITTER CHIP
===============
3.1 BLITMODE TOS CALL
---------------------
Xbios call 64 - Blitmode
flag.w Status
bit 0 - enable
1-14 - reserved
15 - 0 = clear
1 = get
Blitmode 64
trap #14 (tidy #4)
Returns d0.w:
Bit 0 - set (Blit on)
1 - set (If blitter present)
2-14 - reserved
15 - clear
3.2 BLITTER CHIP REGISTERS
--------------------------
Address Length Description
$ff8a00 .w Half tone RAM 0
$ff8a02 .w Half tone RAM 1
$ff8a04 .w Half tone RAM 2
$ff8a06 .w Half tone RAM 3
$ff8a08 .w Half tone RAM 4
$ff8a0a .w Half tone RAM 5
$ff8a0c .w Half tone RAM 6
$ff8a0e .w Half tone RAM 7
$ff8a10 .w Half tone RAM 8
$ff8a12 .w Half tone RAM 9
$ff8a14 .w Half tone RAM 10
$ff8a16 .w Half tone RAM 11
$ff8a18 .w Half tone RAM 12
$ff8a1a .w Half tone RAM 13
$ff8a1c .w Half tone RAM 14
$ff8a1e .w Half tone RAM 15
$ff8a20 .w Source x increment
$ff8a22 .w Source y increment
$ff8a24 .w Source address high word
$ff8a26 .w Source address low word
$ff8a28 .w Endmask 1
$ff8a2a .w Endmask 2
$ff8a2c .w Endmask 3
$ff8a2e .w Destination x increment
$ff8a30 .w Destination y increment
$ff8a32 .w Destination address high word
$ff8a34 .w Destination address low word
$ff8a36 .w x count
$ff8a38 .w y count
$ff8a3a .b Half tone operation (HOP)
$ff8a3b .b Logical operation (OP)
$ff8a3c .b bits 0-3 - Line number
bit 5 - Smudge
bit 6 - HOG
bit 7 - Busy
$ff8a3d .b bits 0-3 - Skew
bit 6 - NFSR
bit 7 - FXSR
3.3 LOGICAL OPERATIONS
----------------------
OP register
Value Result
0 all 0 bits
1 source AND destination
2 source AND NOT destination
3 source
4 NOT source AND destination
5 destination
6 source XOR destination
7 source OR destination
8 NOT source AND NOT destination
9 NOT source XOR destination
10 NOT destination
11 source OR NOT destination
12 NOT source
13 NOT source OR destination
14 NOT source OR NOT destination
15 all 1 bits
3.4 HALF TONE RAM OPERATIONS
----------------------------
HOP register
value operation
0 all 1 bits
1 half tone RAM
2 source
3 source AND half tone RAM
===================
4. CONTROLLER PORTS
===================
4.1 JOYSTICK ADAPTER
--------------------
Pin connections for two joysticks into one STE controller port.
Port A/B Joystick 0/1 Joystick 2/3
1 1 -
2 2 -
3 3 -
4 4 -
5 - -
6 6 -
7 7 7
8 - -
9 8 8
10 - 6
11 - 1
12 - 2
13 - 3
14 - 4
15 - -
4.2 CONTROLLER PORT REGISTERS
-----------------------------
Port A joysticks are 0 and 2, Port B are 1 and 3
Paddles are 0 for Port A, 1 for Port B
$ff9200 xxxx xxxx xxxx 3120 Fire Buttons
$ff9202 UDLR UDLR UDLR UDLR Joystick Direction
Joy3 Joy2 Joy1 Joy0
$ff9210 xxxx xxxx nnnn nnnn Paddle 0 X
$ff9212 xxxx xxxx nnnn nnnn Paddle 0 Y
$ff9214 xxxx xxxx nnnn nnnn Paddle 1 X
$ff9216 xxxx xxxx nnnn nnnn Paddle 1 Y
$ff9220 xxxx xxnn nnnn nnnn Light Pen/Gun X
$ff9222 xxxx xxnn nnnn nnnn Light Pen/Gun Y
UDLR for joysticks 0 and 1 are bi-directional
=============
5. COOKIE JAR
=============
5.1 COOKIE POINTER
------------------
Cookie jar pointer address
$5a0 L p_cookies Pointer to cookie jar
5.2 COOKIE NAMES AND MEANINGS
-----------------------------
Official Atari Cookies:
Name: _CPU
Values: The number here is the decimal value of the last two
digits of the processor present in the machine, indicating which
CPU of the 68000 family it is: 00, 10, 20, 30. For instance, the
value 30 indicates a 68030 processor.
Name: _VDO
Values: The high word of this cookie contains a number from 0
to 2 which indicates what type of video shifter is fitted:
0 - Standard ST video shifter
1 - STE video shifter
2 - TT Graphic Chip
3 - Falcon?
Name: _SND
Values: Here it is the bits which tell us about the sound
hardware. Bit 0 set indicates the presence of a Yamaha sound
chip, bit 1 of the DMA sound chip.
Name: _MCH
Values: This cookie also uses the high word, so that the low
word can be used for version changes, and the value describes the
overall machine:
0 - Standard ST
1 - STE
2 - Mega ST
3 - TT
Name: _SWI
Values: This cookie is used to indicate the positions of the
configuration switches on Mega STEs and TTs. At present these
switches are unused.
Name: _FRB
Values: This longword value will be the address of the fast RAM
buffer, or 0 if no fast RAM buffers are fitted. This cookie is
not found on standard STs or STEs.
