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PlayStation Hacking v1.0 Public
file_id.diz
PlayStation TooL v2.14DS
Texto Referencia R3000
[Build 2.14.02DS 16/Feb/1999]
Version Linux & DOS32
˛http://set.net.eu.org˛ lista
El volumen de la unidad C es TANIT-BIG
El número de serie del volumen es 3214-4536
Directorio de C:\PSX\SET
PS-TL EXE 16/02/99 18:48 PlayStation Tool [SET] DOS
PS-TL ELF 16/02/99 22:48 PlayStation Tool [SET] Linux
PS-TL TXT 17/02/99 21:39 Texto de PSX-Tool
PSX C 17/02/99 20:01 Fuente de PSx-ISO (c) Dc 1995
JP RAW 17/02/99 20:56 Imagen Area Japon [BIOS-8000]
US RAW 17/02/99 20:56 Iamgen Area USA [BIOS-5500]
R3000 TXT 17/02/99 21:21 Texto Mips R3000 *Ingles*
EU RAW 17/02/99 20:55 Imagen Area Europa [BIOS-750HK]
Por razones legales y para evitarnos problemas hemos decidido en ULTIMO momento NO INCLUIR las IMAGENES de los COUNTRY LOCKOUT. Dado que segun lo veo yo son (c) Sony. Si las quereis tendreis que buscar en Internet.
Incluimos las fuentes desde las que se empezo a trabajar para hacer este proyecto, Psx-ISO, son de 95, y son (c) de Damaged Cybernetics. Aviso aun asi que este programa que teneis no es ni mucho menos Psx-ISO, psx-iso no podra actualizar algunos nuevos cds con offsets distintas y patchear el Level-3 de algunos cds nuevos salidos despues de 1996. Avisados estais. cualquier Imagen en FORMATO RAW, funcionara corectamente. Fijaros en los tama§os, si no son iguales no son las correctas!!!
SET.1999!
ps-tl
SET I+D - 1999 - PlayStation Hacking v1.0 Public
(c) SET I+D
* Version Final * Linux & DOS - 16 de Febrero 1999 *
®Que hace ?
Parchea una ISO9660 de PSX con imagenes "nuevas" de los paises. Te permite tener imagenes que luego podr†s grabar y jugar a el juego sin chip *siempre y cuando* hayas grabado ese cd en una grabadora *con FIRMWARE/ROM* previamente preparada para no corregir los errores de las ISOs de PSX. Estas isos son grabadas de la "manera adecuada" y ejecutadas en "cualquier" PSX ya tenga "chip" o no, funcionara el juego siempre que la version del cd sea la correcta a esa PSX. No digais que os hemos enga§ado por que un cd hecho con esto no arranca en una psx de un pais distinto al suyo si esta no tiene chip. Este programa tiene su base en una que salio en el 95 por Damaged Cybernetics (Dc) del que incluimos las fuentes, aviso que esto compilado NO HACE lo mismo que PS-Tool, la rutinas son distintas.. Psxiso puede funcionar con isos creadas *solo* de cds comerciales, es decir no puedes crear la tuya. Incluimos las fuentes para que si quereis trabajeis en esto y podais llegar a *incluso* desprotejer el check de *soft* que tengan las isos, dado que se puede detectar. Y como nosotros no trabajamos para que LUEGO LA GENTE SE DEDIQUE A LA PIRATERIA PURA Y DURA , Pues nos hemos visto obligados a replantearnos dar *todas* las fuentes del programa y simplemente dar un programa que es LEGAL y sin mas conocimientos no hace nada.
Tabla de compatibilidad....
^^^^^^^^^^^^^^^^^^^^^^^^^^^
CDUSA + PSUSA = OK!
CDUSA + PSUSA + CHIP = OK!
CDPAL + PSUSA = NO
CDPAL + PSUSA + CHIP = OK!
CDJAP + PSUSA = NO
CDJAP + PSUSA + CHIP = OK!
CDPAL + PSPAL = OK!
CDPAL + PSPAL + CHIP = OK!
CDUSA + PSPAL + CHIP = OK!
CDUSA + PSPAL = NO
CDJAP + PSPAL = NO
CDJAP + PSPAL + CHIP = OK!
CDJAP + PSJAP = OK!
CDJAP + PSJAP + CHIP = OK!
CDUSA + PSJAP + CHIP = OK!
CDUSA + PSJAP = NO
CDPAL + PSJAP + CHIP = OK!
CDPAL + PSJAP = NO
CDJAP + PS7501C(Jap) = OK!
* CDUSA + PS7501C(Usa) = OK! (Usa el sentido común si te queda!)
CDPAL + PS7501C(Pal) = OK!
CDPAL/JAP/USA + SCSI-PSEMU = OK!
** CDPAL/JAP/USA + PSXXX + ACTION REPLAY = OK!
** El Action Replay necesita una ROM Hackeada para que funcione desde una unidad de cd-rom de pc ** Esas como os podeis imaginar si tienes un CDPal y la 7501C es JAP/US no habra manera humana de hacer funcionar el CD, pero para eso esta esta utilidad aqui.. Tambien algunos cd AUNQUE SEAN CORRECTOS, no funcionar†n dado que algunos Chips no estan bien instalados o no son los correctos y simplemente no arrancar†n. Yo de todo esto no puedo ser el culpable.... Algunos Chips te permiten arrancar cd-rs pero si esta mal instalado en una Pal *puede* ocurrir que la consola no sea capaz de arrancar CDs originales de PlayStation PAL NUNCA MAS!
Pero esta arranque perfectamente cd-r/silver Jap/Us, yo he visto unas cuantas. Cuidadin con que Chip le pones..
Donde PSPAL/USA/JAP puede ser cualquier revision de la Bios, 100x, 200x, etc.. o la que te de la gana. Esto esta en la pegatina de debajo de la play.
_ _
____(_)___(_)_____
Ô. .`
| |
| SCHP-XXXXX |
| | Mira tu Version de la Bios, tambien
| . .| esta en la placa...
`--||--o-----\----Ô
Ejemplo:
ps-tl rrhack.iso jp.raw 0 Convertiria la iso de la version hackeada del Ridge Racer I a un cd para usar con una PSX Japonesa. Aplicando el PATCH desde el principio de la ISO (0) dado que es una ISO sin header de ningun tipo. El resto es algo que casi se explica solo. Experimentad...
Sobre el programa..
Esta es la unica versi¢n que saldra,*FINAL*, SET staff o ninguno de los miembros del staff *respondera* a ninguna pregunta relacionada con esto. Este programa mejora a las versiones anteriores y los ficheros de los paises son distintos a los que hay por ahi en internet. Parte del codigo fue tomado de Damaged Cybernetics, gracias a Mindrape, por hacer las fuentes libres, otra parte proviene de HongKong CuD y una utilidad que hicieron para su uso interno. Gracias a ellos tambien. Nuestro programa a§ade cosas nuevas a la rutina y soporte para algunas ISOs que los anteriores no tenian, isos de algunos programas no hace falta quitarles el header y es automatico. Este programa no se da acompa§ado de sus fuentes dado que con pocos cambios se podria hacer una utilidad para la COPIA MASIVA Y DESPROTECCION de las ISOS de PlayStation y como este NO ES NUESTRO OBJETIVO, pues no hemos visto obligados a quitarle algunas opciones potencialmente peligrosas. Este programa aun asi, con los conocimientos suficientes puede ayudar a hacer cds que son copias perfectas de playstation, pero dada su dificultad (esto se podia haber hecho hace muucho!) no es ningun peligro que esta utilidad salga a la luz. Si estas leyendo esto es que ha salido como version publica.
˛ No se distribuira "nuestra" version en tipo GPL...
˛ SET o SET I+D *NO ALENTAN LA PIRATERIA DE **NINGUNA** MANERA...
˛ Usas esto a TU PROPIA CUENTA Y RIESGO... ÔAS IT ISÔ
SET I+D
Saqueadores Edici¢n TÇcnica I+D (c) 1999
PlayStation & PSX son marcas registradas de Sony.
psx.c
#include <stdio.h>
#include <stdlib.h>
/* prototypes */
char PSXPatch(char *szFileName,char *szCountryPatch,unsigned long ulSkipBytes);
void help();
/* general definitions */
#define BUFFER_SIZE 4096
#define TRUE 1
#define FALSE 0
/*
char PSXPatch(char *szFilename,char *szCountryPatch,unsigned long ulSkipBytes)
ENT: char *szFileName - ISO Image filename to patch
char *szCountryPatch - Country Code Lockout Patch
unsigned long ulSkipBytes - Bytes to skip in case of ISO Header
RET: TRUE - Patching was successful
FALSE - Patching was unsuccessful
Read szCountryPatch and patch the first 5 sectors (0-4) of the ISO Image.
Skip ulSkipBytes to bypass any possible headers, but normally this is
0.
*/
char PSXPatch(char *szFilename,char *szCountryPatch,unsigned long ulSkipBytes)
{ FILE *dest; /* our destination file */
FILE *patch; /* our country code lockout patch */
unsigned char acBuffer[BUFFER_SIZE]; /* buffer to hold our patch */
unsigned int uiFileSize; /* keep track of the bytes we copy from patch */
/* open our destination file and our patch file */
if ((dest = fopen(szFilename,"r+b")) == NULL)
{
printf("Cannot open input file: %s\n",szFilename);
return(FALSE);
}
if ((patch = fopen(szCountryPatch,"rb")) == NULL)
{
printf("Cannot open input file: %s\n",szCountryPatch);
return(FALSE);
}
/* now skip ulSkipBytes, users will need to skip any ISO image
headers that may exist.
*/
fseek(dest,ulSkipBytes,SEEK_SET);
/* now copy the patch over the first 5 sectors of the REAL PSX image */
while (!feof(patch))
{
uiFileSize = fread(acBuffer,1,BUFFER_SIZE,patch);
fwrite(acBuffer,1,uiFileSize,dest);
}
fcloseall(); /* close everything down */
return(TRUE);
}
void help(void)
{
printf("PSX Immigrator was designed to patch PSX ISO Images with the correct\n"
"Country Code Lock patch. It does not recognize Win'95 Long File Names.\n\n"
"Usage: PSXISO <source.iso> <patch.raw> <starting offset>\n\n"
"source.iso - PSX ISO Image\n"
"patch.raw - Country Code Lockout\n"
"starting offset - Start Location of the REAL PSX ISO images."
);
}
void main(int argc,char *argv[])
{
puts("PSX Immigrator Version 1.0\n(C) 1995 Damaged Cybernetics (www.goodnet.com/~staheli)\n");
if (argc < 4)
{
help();
exit(1);
}
printf("Patching %s.\n"
"Using %s as a Country Code Lockout patch.\n"
"Skipping %u bytes...\n",argv[1],argv[2],atol(argv[3])
);
if (PSXPatch(argv[1],argv[2],atol(argv[3])))
puts("Successful Patch.");
else
puts("Unsuccessful patch.");
}
r3000
[Texto sobre MIPS, utils a la hora de hacer debug de PS-EXEs ]
[Distribuido con SET - Hacking PlayStation - 16/Feb/99 ]
[Saqueadores Edici¢n TÇcnica - SET ˛http://set.net.eu.org˛ ]
[SET I+D - Keep on Hacking! - ]
Description of the Machine
^^^^^^^^^^^^^^^^^^^^^^^^^^
A MIPS processor consists of an integer processing unit (the CPU) and
a collection of coprocessors that perform ancillary tasks or operate
on other types of data such as floating point numbers.
SPIM simulates two coprocessors. Coprocessor 0 handles traps,
exceptions, and the virtual memory system. SPIM simulates most of
the first two and entirely omits details of the memory system.
Coprocessor 1 is the floating point unit. SPIM simulates most aspects
of this unit.
CPU Registers
^^^^^^^^^^^^^
Register Name Number Usage
zero 0 Constant 0
at 1 Reserved for assembler
v0 2 Expression evaluation and
v1 3 results of a function
a0 4 Argument 1
a1 5 Argument 2
a2 6 Argument 3
a3 7 Argument 4
t0 8 Temporary (not preserved across call)
t1 9 Temporary (not preserved across call)
t2 10 Temporary (not preserved across call)
t3 11 Temporary (not preserved across call)
t4 12 Temporary (not preserved across call)
t5 13 Temporary (not preserved across call)
t6 14 Temporary (not preserved across call)
t7 15 Temporary (not preserved across call)
s0 16 Saved temporary (preserved across call)
s1 17 Saved temporary (preserved across call)
s2 18 Saved temporary (preserved across call)
s3 19 Saved temporary (preserved across call)
s4 20 Saved temporary (preserved across call)
s5 21 Saved temporary (preserved across call)
s6 22 Saved temporary (preserved across call)
s7 23 Saved temporary (preserved across call)
t8 24 Temporary (not preserved across call)
t9 25 Temporary (not preserved across call)
k0 26 Reserved for OS kernel
k1 27 Reserved for OS kernel
gp 28 Pointer to global area
sp 29 Stack pointer
fp 30 Frame pointer
ra 31 Return address (used by function call)
MIPS registers and the convention governing their use.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The MIPS (and SPIM) central processing unit contains 32 general
purpose registers that are numbered 0--31.
Register n is designated by $n.
Register $0 always contains the hardwired value 0.
MIPS has established a set of conventions how the registers should be used.
These suggestions are guidelines, which are not enforced by the hardware.
However a program that violates them will not work properly with other
software.
List II - The registers and describes their intended use.
Registers $at (1), $k0 (26), and $k1 (27) are reserved for use by
the assembler and operating system.
Registers $a0--$a3 (4--7) are used to pass the first four arguments
to routines (remaining arguments are passed on the stack).
Registers $v0 and $v1 (2, 3) are used to return values from functions.
Registers $t0--$t9 (8--15, 24, 25) are caller-saved registers used
for temporary quantities that do not need to be preserved across calls.
Registers $s0--$s7 (16--23) are callee-saved registers that hold
long-lived values that should be preserved across calls.
Register $sp (29) is the stack pointer, which points to the first
free location on the stack.
Register $fp (30) is the frame pointer.
(The MIPS compiler does not use a frame pointer, so this register is
used as callee-saved register $s8.)
Register $ra (31) is written with the return address for a call by
the jal instruction.
Register $gp (28) is a global pointer that points into the
middle of a 64K block of memory in the heap that holds constants
and global variables. The objects in this heap can be quickly
accessed with a single load or store instruction.
In addition, coprocessor 0 contains registers that are used for
exception handling. SPIM does not implement all of these registers,
since they are not of much use in a simulator (or are part of the
memory system). However, it does provide the following:
Register Name Number Usage
^^^^^^^^^^^^^ ^^^^^^ ^^^^^^
BadVAddr 8 Memory address at which address exception occurred
Status 12 Contains interrupt enable bits
Cause 13 Type of exception
EPC 14 Address of instruction that caused exception
These registers are part of coprocessor 0's register set and can
be accessed by the lwc0, mfc0, mtc0, and swc0 instructions.
Byte Order
^^^^^^^^^^
Processors can number the bytes within a word to make the byte
with the lowest numer either the leftmost or rightmost one.
The convention used by a machine is its byte order.
MIPS processors can operate with either big-endian byte order:
Byte #
0 1 2 3
or little-endian byte order:
Byte #
3 2 1 0
SPIM also operates with both byte orders.
SPIM's byte order is determined by the byte order of the
underlying hardware that is running the simulator.
On a DECstation 3100, SPIM is little-endian, while on a HP Bobcat,
Sun 4 or PC/RT, SPIM is big-endian.
Addressing Modes
^^^^^^^^^^^^^^^^
MIPS is a load/store architecture, which means that only load and
store instructions access memory. Computation instructions operate
only on values in registers. The bare machine provides only one
memory addressing mode: c(rx), which uses the sum of the immediate
(integer) c and the contents of register rx as the address.
The virtual machine provides the following addressing modes for load
and store instructions:
Format Address Computation
^^^^^^ ^^^^^^^ ^^^^^^^^^^^
(register) contents of register
imm immediate
imm (register) immediate + contents of register
symbol address of symbol
symbol +/- imm address of symbol + immediate
symbol +/- imm (register) address of symbol + ( " + contents of register)
Most load and store instructions operate only on aligned data.
A quantity is aligned if its memory address is a multiple of its
size in bytes. Therefore, a halfword object must be stored at
even addresses and a full word object must be stored at addresses
that are a multiple of 4. However, MIPS provides someinstructions
for manipulating unaligned data.
Load and Store Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^^
la Rdest, address Load Address
Load computed address, not the contents of the location into register Rdest.
lb Rdest, address Load Byte
lbu Rdest, address Load Unsigned Byte
Load the byte at address into register Rdest (and sign-extend it).
ld Rdest, address Load Double-Word
Load the 64-bit quantity at address into registers Rdest and Rdest + 1.
lh Rdest, address Load Halfword
lhu Rdest, addressLoad Unsigned Halfword
Load the 16-bit quantity (halfword) at address into register Rdest
(and sign-extend it).
lw Rdest, address Load Word
Load the 32-bit quantity (word) at address into register Rdest.
lwcz Rdest, address Load Word Coprocessor
Load the word at address into register Rdest of coprocessor z (0--3).
lwl Rdest, address Load Word Left
lwr Rdest, address Load Word Right
Load the left (right) bytes from the word at the possibly-unaligned
address into register Rdest.
sb Rsource, address Store Byte
Store the low byte from register Rsource at address.
sd Rsource, address Store Double-Word
Store the 64-bit quantity in registers Rsource and Rsource + 1 at address.
sh Rsource, address Store Halfword
Store the low halfword from register Rsource at address.
sw Rsource, address Store Word
Store the word from register Rsource at address.
swcz Rsource, address Store Word Coprocessor
Store the word from register Rsource of coprocessor z at address.
swl Rsource, address Store Word Left
swr Rsource, address Store Word Right
Store the left (right) bytes from register Rsource at the
possibly-unaligned address.
ulh Rdest, address Unaligned Load Halfword
ulhu Rdest, address Unaligned Load Halfword Unsigned
Load the 16-bit quantity (halfword) at the possibly-unaligned address
into register Rdest (and sign-extend it).
ulw Rdest, address Unaligned Load Word
Load the 32-bit quantity (word) at the possibly-unaligned address
into register Rdest.
ush Rsource, address Unaligned Store Halfword
Store the low halfword from register Rsource at the possibly-unaligned
address.
usw Rsource, address Unaligned Store Word
Store the word from register Rsource at the possibly-unaligned address.
Exception and Trap Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
rfe Return From Exception
Restore the Status register.
syscall System Call
Register $v0 contains the number of the system call
break nBreak
Cause exception n. Exception 1 is reserved for the debugger.
nop No operation
Do nothing.
(Nota de SET, tomad nota de lo que hay x aqui....)
Constant-Manipulating Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
li Rdest, imm Load Immediate
Move the immediate into register Rdest.
li.d FRdest, float Load Immediate Double
Move the double-precision floating point number into floating
point registers FRdest and FRdest + 1.
li.s FRdest, float Load Immediate Single
Move the single-precision floating point number into floating
point register FRdest.
lui Rdest, integer Load Upper Immediate
Load the lower halfword of the integer into the upper halfword
of register Rdest. The lower bits of the register are set to 0.
Arithmetic and Logical Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
In all instructions below, Src2 can either be a register or an
immediate value (integer). The immediate forms of the instructions
are only included for reference. The assembler will translate the
more general form of an instruction (e.g., add) into the immediate
form (e.g., addi) if the second argument is constant.
abs Rdest, Rsource Absolute Value
Put the absolute value of the integer from register Rsource in
register Rdest.
add Rdest, Rsrc1, Src2 Addition (with overflow)
addi Rdest, Rsrc1, Imm Addition Immediate (with overflow)
addu Rdest, Rsrc1, Src2 Addition (without overflow)
addiu Rdest, Rsrc1, Imm Addition Immediate (without overflow)
Put the sum of the integers from register Rsrc1 and Src2 (or Imm)
into register Rdest.
and Rdest, Rsrc1, Src2 AND
andi Rdest, Rsrc1, Imm AND Immediate
Put the logical AND of the integers from register Rsrc1 and Src2
(or Imm) into register Rdest.
div Rsrc1, RSrc2 Divide (with overflow)
divu Rsrc1, RSrc2 Divide (without overflow)
Divide the contents of the two registers. Leave the quotient
in register LO and the remainder in register HI. Note that if
an operand is negative, the remainder is unspecified by the MIPS
architecture and depends on the conventions of the machine on
which SPIM is run.
div Rdest, Rsrc1, Src2 Divide (with overflow)
divu Rdest, Rsrc1, Src2 Divide (without overflow)
Put the quotient of the integers from register Rsrc1 and Src2
into register Rdest.
mul Rdest, Rsrc1, Src2 Multiply (without overflow)
mulo Rdest, Rsrc1, Src2 Multiply (with overflow)
mulou Rdest, Rsrc1, Src2 Unsigned Multiply (with overflow)
Put the product of the integers from register Rsrc1 and Src2 into
register Rdest.
mult Rsrc1, RSrc2 Multiply
multu Rsrc1, RSrc2 Unsigned Multiply
Multiply the contents of the two registers. Leave the low-order
word of the product in register LO and the high-word in register HI.
neg Rdest, Rsource Negate Value (with overflow)
negu Rdest, Rsource Negate Value (without overflow)
Put the negative of the integer from register Rsource into register Rdest.
nor Rdest, Rsrc1, Src2 NOR
Put the logical NOR of the integers from register Rsrc1 and Src2
into register Rdest.
not Rdest, Rsource NOT
Put the logical negation of the integer from register Rsource into
register Rdest.
or Rdest, Rsrc1, Src2 OR
ori Rdest, Rsrc1, Imm OR Immediate
Put the logical OR of the integers from register Rsrc1 and Src2
(or Imm) into register Rdest.
rem Rdest, Rsrc1, Src2 Remainder
remu Rdest, Rsrc1, Src2 Unsigned Remainder
Put the remainder from dividing the integer in register Rsrc1 by
the integer in Src2 into register Rdest. Note that if an operand
is negative, the remainder is unspecified by the MIPS architecture
and depends on the conventions of the machine on which SPIM is run.
rol Rdest, Rsrc1, Src2 Rotate Left
ror Rdest, Rsrc1, Src2 Rotate Right
Rotate the contents of register Rsrc1 left (right) by the distance
indicated by Src2 and put the result in register Rdest.
sll Rdest, Rsrc1, Src2 Shift Left Logical
sllv Rdest, Rsrc1, Rsrc2 Shift Left Logical Variable
sra Rdest, Rsrc1, Src2 Shift Right Arithmetic
srav Rdest, Rsrc1, Rsrc2 Shift Right Arithmetic Variable
srl Rdest, Rsrc1, Src2 Shift Right Logical
srlv Rdest, Rsrc1, Rsrc2 Shift Right Logical Variable
Shift the contents of register Rsrc1 left (right) by the distance
indicated by Src2 (Rsrc2) and put the result in register Rdest.
sub Rdest, Rsrc1, Src2 Subtract (with overflow)
subu Rdest, Rsrc1, Src2 Subtract (without overflow)
Put the difference of the integers from register Rsrc1 and Src2
into register Rdest.
xor Rdest, Rsrc1, Src2 XOR
xori Rdest, Rsrc1, Imm XOR Immediate
Put the logical XOR of the integers from register Rsrc1 and
Src2 (or Imm) into register Rdest.
Comparison Instructions
^^^^^^^^^^^^^^^^^^^^^^^
In all instructions below, Src2 can either be a register or
an immediate value (integer).
seq Rdest, Rsrc1, Src2 Set Equal
Set register Rdest to 1 if register Rsrc1 equals Src2 and to be 0 otherwise.
sge Rdest, Rsrc1, Src2 Set Greater Than Equal
sgeu Rdest, Rsrc1, Src2 Set Greater Than Equal Unsigned
Set register Rdest to 1 if register Rsrc1 is greater than or equal
to Src2 and to 0 otherwise.
sgt Rdest, Rsrc1, Src2 Set Greater Than
sgtu Rdest, Rsrc1, Src2 Set Greater Than Unsigned
Set register Rdest to 1 if register Rsrc1 is greater than Src2
and to 0 otherwise.
sle Rdest, Rsrc1, Src2 Set Less Than Equal
sleu Rdest, Rsrc1, Src2 Set Less Than Equal Unsigned
Set register Rdest to 1 if register Rsrc1 is less than or equal
to Src2 and to 0 otherwise.
slt Rdest, Rsrc1, Src2 Set Less Than
slti Rdest, Rsrc1, Imm Set Less Than Immediate
sltu Rdest, Rsrc1, Src2 Set Less Than Unsigned
sltiu Rdest, Rsrc1, Imm Set Less Than Unsigned Immediate
Set register Rdest to 1 if register Rsrc1 is less than Src2 (or Imm)
and to 0 otherwise.
sne Rdest, Rsrc1, Src2 Set Not Equal
Set register Rdest to 1 if register Rsrc1 is not equal to Src2 and
to 0 otherwise.
Branch and Jump Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
In all instructions below, Src2 can either be a register or an
immediate value (integer). Branch instructions use a signed 16-bit
offset field; hence they can jump 215-1 instructions (not bytes)
forward or 215 instructions backwards. The jump instruction
contains a 26 bit address field.
b label Branch instruction
Unconditionally branch to the instruction at the label.
bczt label Branch Coprocessor z True
bczf label Branch Coprocessor z False
Conditionally branch to the instruction at the label if coprocessor
z's condition flag is true (false).
beq Rsrc1, Src2, label Branch on Equal
Conditionally branch to the instruction at the label if the contents
of register Rsrc1 equals Src2.
beqz Rsource, label Branch on Equal Zero
Conditionally branch to the instruction at the label if the contents
of Rsource equals 0.
bge Rsrc1, Src2, label Branch on Greater Than Equal
bgeu Rsrc1, Src2, label Branch on GTE Unsigned
Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are greater than or equal to Src2.
bgez Rsource, label Branch on Greater Than Equal Zero
Conditionally branch to the instruction at the label if the contents
of Rsource are greater than or equal to 0.
bgezal Rsource, label Branch on Greater Than Equal Zero And Link
Conditionally branch to the instruction at the label if the contents
of Rsource are greater than or equal to 0. Save the address of the next instruction in register 31.
bgt Rsrc1, Src2, label Branch on Greater Than
bgtu Rsrc1, Src2, label Branch on Greater Than Unsigned
Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are greater than Src2.
bgtz Rsource, label Branch on Greater Than Zero
Conditionally branch to the instruction at the label if the contents
of Rsource are greater than 0.
ble Rsrc1, Src2, label Branch on Less Than Equal
bleu Rsrc1, Src2, label Branch on LTE Unsigned
Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are less than or equal to Src2.
blez Rsource, label Branch on Less Than Equal Zero
Conditionally branch to the instruction at the label if the contents
of Rsource are less than or equal to 0.
bgezal Rsource, label Branch on Greater Than Equal Zero And Link
bltzal Rsource, label Branch on Less Than And Link
Conditionally branch to the instruction at the label if the contents
of Rsource are greater or equal to 0 or less than 0, respectively.
Save the address of the next instruction in register 31.
blt Rsrc1, Src2, label Branch on Less Than
bltu Rsrc1, Src2, label Branch on Less Than Unsigned
Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are less than Src2.
bltz Rsource, label Branch on Less Than Zero
Conditionally branch to the instruction at the label if the contents
of Rsource are less than 0.
bne Rsrc1, Src2, label Branch on Not Equal
Conditionally branch to the instruction at the label if the contents
of register Rsrc1 are not equal to Src2.
bnez Rsource, label Branch on Not Equal Zero
Conditionally branch to the instruction at the label if the contents
of Rsource are not equal to 0.
j label Jump
Unconditionally jump to the instruction at the label.
jal labelJump and Link
jalr Rsource Jump and Link Register
Unconditionally jump to the instruction at the label or whose address
is in register Rsource. Save the address of the next instruction in
register 31.
jr Rsource Jump Register
Unconditionally jump to the instruction whose address is in register Rsource.
Data Movement Instructions
^^^^^^^^^^^^^^^^^^^^^^^^^^
move Rdest, Rsource Move
Move the contents of Rsource to Rdest.
The multiply and divide unit produces its result in two additional
registers, HI and LO. These instructions move values to and from
these registers. The multiply, divide, and remainder instructions
described above are pseudo instructions that make it appear as if
this unit operates on the general registers and detect error
conditions such as divide by zero or overflow.
mfhi Rdest Move From HI
mflo Rdest Move From LO
Move the contents of the HI (LO) register to register Rdest.
mthi Rdest Move To HI
mtlo Rdest Move To LO
Move the contents register Rdest to the HI (LO) register.
Coprocessors have their own register sets. These instructions move
values between these registers and the CPU's registers.
mfcz Rdest, Copsource Move From Coprocessor z
Move the contents of coprocessor z's register Copsource to CPU
register Rdest.
mfc1.d Rdest, FRsrc1 Move Double From Coprocessor 1
Move the contents of floating point registers FRsrc1 and FRsrc1 +
1 to CPU registers Rdest and Rdest + 1.
mtcz Rsource, Copdest Move To Coprocessor z
Move the contents of CPU register Rsource to coprocessor z's
register Copdest.
Floating Point
^^^^^^^^^^^^^^^
The MIPS has a floating point coprocessor (numbered 1) that operates
on single precision (32-bit) and double precision (64-bit) floating
point numbers. This coprocessor has its own registers, which are
numbered $f0--$f31. Because these registers are only 32-bits wide,
two of them are required to hold doubles. To simplify matters,
floating point operations only use even-numbered registers---including
instructions that operate on single floats.
Values are moved in or out of these registers a word (32-bits) at a
time by lwc1, swc1, mtc1, and mfc1 instructions described above or by
the l.s, l.d, s.s, and s.d pseudo instructions described below.
The flag set by floating point comparison operations is read by the
CPU with its bc1t and bc1f instructions.
In all instructions below, FRdest, FRsrc1, FRsrc2, and FRSource are
floating point registers (e.g., $f2).
abs.d FRdest, FRsource Floating Point Absolute Value Double
abs.s FRdest, FRsource Floating Point Absolute Value Single
Compute the absolute value of the floating float double (single) in
register FRsource and put it in register FRdest.
add.d FRdest, FRsrc1, FRsrc2 Floating Point Addition Double
add.s FRdest, FRsrc1, FRsrc2 Floating Point Addition Single
Compute the sum of the floating float doubles (singles) in registers
FRsrc1 and FRsrc2 and put it in register FRdest.
c.eq.d FRsrc1, FRsrc2 Compare Equal Double
c.eq.s FRsrc1, FRsrc2 Compare Equal Single
Compare the floating point double in register FRsrc1 against the one
in FRsrc2 and set the floating point condition flag true if they are equal.
c.le.d FRsrc1, FRsrc2 Compare Less Than Equal Double
c.le.s FRsrc1, FRsrc2 Compare Less Than Equal Single
Compare the floating point double in register FRsrc1 against the
one in FRsrc2 and set the floating point condition flag true if
the first is less than or equal to the second.
c.lt.d FRsrc1, FRsrc2 Compare Less Than Double
c.lt.s FRsrc1, FRsrc2 Compare Less Than Single
Compare the floating point double in register FRsrc1 against the
one in FRsrc2 and set the condition flag true if the first is less
than the second.
cvt.d.s FRdest, FRsource Convert Single to Double
cvt.d.w FRdest, FRsource Convert Integer to Double
Convert the single precision floating point number or integer in
register FRsource to a double precision number and put it in
register FRdest.
cvt.s.d FRdest, FRsource Convert Double to Single
cvt.s.w FRdest, FRsource Convert Integer to Single
Convert the double precision floating point number or integer in
register FRsource to a single precision number and put it in
register FRdest.
cvt.w.d FRdest, FRsource Convert Double to Integer
cvt.w.s FRdest, FRsource Convert Single to Integer
Convert the double or single precision floating point number
in register FRsource to an integer and put it in register FRdest.
div.d FRdest, FRsrc1, FRsrc2 Floating Point Divide Double
div.s FRdest, FRsrc1, FRsrc2 Floating Point Divide Single
Compute the quotient of the floating float doubles (singles) in
registers FRsrc1 and FRsrc2 and put it in register FRdest.
l.d FRdest, address Load Floating Point Double
l.s FRdest, address Load Floating Point Single
Load the floating float double (single) at address into register FRdest.
mov.d FRdest, FRsource Move Floating Point Double
mov.s FRdest, FRsource Move Floating Point Single
Move the floating float double (single) from register FRsource
to register FRdest.
mul.d FRdest, FRsrc1, FRsrc2 Floating Point Multiply Double
mul.s FRdest, FRsrc1, FRsrc2 Floating Point Multiply Single
Compute the product of the floating float doubles (singles) in
registers FRsrc1 and FRsrc2 and put it in register FRdest.
neg.d FRdest, FRsource Negate Double
neg.s FRdest, FRsource Negate Single
Negate the floating point double (single) in register FRsource
and put it in register FRdest.
s.d FRdest, address Store Floating Point Double
s.s FRdest, address Store Floating Point Single
Store the floating float double (single) in register FRdest at address.
sub.d FRdest, FRsrc1, FRsrc2 Floating Point Subtract Double
sub.s FRdest, FRsrc1, FRsrc2 Floating Point Subtract Single
Compute the difference of the floating float doubles (singles)
in registers FRsrc1 and FRsrc2 and put it in register FRdest.
[EOF!] 
