N64d (v0.2) - Register definitions for the above
R4300 CP0 Registers
Researched by Andy Simpson
Source:(http://www.sgi.com)
Below are all CP0 registers used in the R4300. We don't know what might happen if you attempted to write to any of the registers marked as "unused", but let's face it, it can't be healthy! The same goes for reading any "unused" register. Basically, the read or write will be undefined and therefore data will be unpredictable to say the least.
This information is also available from www.sgi.com (our source). However, the text on that particular site is heavily condensed. Nb, this doc does not come with register diagrams/tables. These are available from the above site (although text is VERY difficult to read). Future versions of this document will contain the missing diagrams (with comprehendable labels!). Before reading on, it is recommended you take a look at CP0.doc as this explains some abbreviations and terminology used in this document. Okay for you?
System Control CP0 Registers
Number Mnemonic Description
00 Index Programmable pointer into TLB array
01 Random Random pointer into TLB array
02 EntryLo0 Low half of the TLB entry for even VPN
03 EntryLo1 Low half of the TLB entry for odd VPN
04 Context Pointer to kernel PTE table
05 PageMask TLB page mask
06 Wired Number of wire TLB entries
07 N/A Unused
08 BadVAddr Bad virtual address
09 Count Timer count
10 EntryHi High half of TLB entry
11 Compare Timer compare
12 SR Status register
13 Cause Cause register
14 EPC Exception program counter
15 PRid Processor revision identifier
16 Config Configuration register
17 LLAddr Load linked address
18 WatchLo Memory reference trap address lower bits
19 WatchHi Memory reference trap address upper bits
20 XContext Context register for MIPS-III addressing
21-25 N/A Unused
26 PErr Not Used
27 CacheErr Not Used
28 TagLo Cache tag register
29 TagHi Cache tag register (Reserved)
30 ErrorEPC Error exception program counter
31 N/A Unused
Definition of registers
The Index register is a read/write register in which 6 bits specify an entry to the on-chip TLB. The high order bit indicates success/failure of TLBP operations. The TLB Index register is used to specify the entry in the TLB affected by the TLBR and TLBWI instructions.
The Random register is read-only. 6 bits specify an entry in the on-chip TLB. This register will decrease upon every executed instruction. The value range is between a low value (determined by the TLB Wired register), and an upper bound of TLBENTRIES-1. The TLB Random register is used to specify the entry in the TLB affected by the TLBWR instruction. This register will be set to the upper limit should the system be reset, or when/if the Wired register is written.
The EntryLo0 and EntryLo1 registers are a read/write register pair. They can be classed together as they are both used to access on-chip TLB. EntryLo0 is used for even virtual pages while EntryLo1 is used for odd virtual pages. The Page Frame Number, along with several configuration bits for the TLB entry are contained therein. These registers are used by the TLBR, TLBWI, and TLBWR instructions.
The Context register is also a read/write register, this time containing a pointer into a kernel PTE (Page Table Entry) array. Its design purpose is for use in the TLB refill handler. note that the the BadVPN2 field is not writable - it contains the VPN of the most recently translated virtual address that didn't have a valid translation. Bits 31:13 of the virtual address (that caused the TLB miss) are contained here. Bit 12 is excluded because a single TLB entry maps an even-odd page pair. This format can be used directly as an address for pages 4KB in size. For all other page sizes the value has to be shifted and masked. The PTE Base field is both readalble and writeable writable and gives indication of the base address of the PTE table of the current user address space (phew!).
The PageMask register is both readable and writeable. It is used when reading/writing to an on-chip TLB. The TLBR, TLBWI, and TLBWR instructions use this register as a source or a destination. When virtual addresses undergo translation, the corresponding bits in the TLB specify which of virtual address bits 24.13 occur in the comparison. This allows for a variable page size per entry. These pages can be 4K, 16K, 64K, 256K, 1M, 4M or 16M in size.
The TLB Wired register is a read/write register specifying the boundary between the wired and random entries of the TLB. Upon reset, this register is set to zero. Writing to this register will set the Random register to 31. Writing a value greater than TLBENTRIES-1 will probably cause something to go haywire, so don't even bother!
The Bad Virtual Address register is read-only. It displays the virtual address most recently translated which either a) failed to have a valid translation or b) had an addressing error.
The Count register is a read/write register used with timer services. It increases constantly at a rate based on the clock cycle. When it has reached all ones, it will zero itself and continue counting.
The EntryHi register is both readable and writeable. It is used to access on-chip TLB. The TLBR, TLBWI, and TLBWR instructions all use this register. EntryHi contains the ASID (Address Space Identifier) and the Virtual Page Number.
The Compare register is a read/write register. When the value of the Count register is equal to that of the Compare register, IP7 of the Cause register is set. This causes an interrupt on the next (interrupt-enabled) execution cycle. Upon writing to the Compare register, the timer interrupt will be cleared.
The Status register is a read/write register. It contains the mode, enable, and status bits used on the R300i processor. The contents of this register are undefined after a reset, with the exception of TS, which is zero, ERL and BEV, which equal one and RP, which is also zero. The SR bit is 0 after a Cold Reset, and 1 after NMI or a Soft Reset.
The Cause register is a readable and writeable register that describes the last exception. A 5-bit exception code details the cause of the exception and the rest of the fields contain detailed exception handling information. The Branch Delay bit indicates if the EPC has been adjusted to point at the branch instruction which precedes the next restartable instruction. The Coprocessor Error field indicates the unit number referenced by an instruction causing what is known as a Coprocessor Unusable exception. The IP field indicates which interrupts are pending - this field indicates the current status and changes in response to external signals. IP7 is the timer interrupt bit which is set when the Count register is equal to the Compare register. IP6:2 are external interrupts which are set when the external interrupts are signalled. An external interrupt is set at one of the external interrupt pins or through a write request on the SysAD bus. IP1:0 are software interrupts and may be written to set (or clear) software interrupts.
The EPC register is a read and write register containing the address at which instruction processing can resume after an exception. For synchronous exceptions, the EPC register contains the virtual address of the instruction (the direct cause of the exception), or (when that instruction is in a branch delay slot), the EPC contains the virtual address of the immediately preceding branch or jump instruction and sets the Branch Delay bit in the Cause register. If the exception is caused by a non-fatal, recoverable condition, the EPC contains the virtual address of the instruction which caused the exception. After correcting the conditions, the EPC contains a point at which execution can be safely resumed.
The PRId register is read-only. Unfortunately, we have no other information on it at present. Tch! Disgraceful!
The Config register specifies various configuration options for the processor. The EP and BE fields are writable only by software. The CU and K0 fields are both readable and writable by software. There is no other way to write to these fields. After Reset their values become undefined.
The WatchHi/WatchLo register pair are used as a debugging feature to detect references to a physical address. Loads/stores to the location specified by the registers cause a Watch trap.
The LLAddr register both readable and writable, but by software only. Itcontains the physical address read by the most recent Load Linked instruction. Not quite sure what its practical function would be, except for within diagnostics maybe..... Help?
The XContext register is a read and writeable. It contains a pointer into a kernel PTE array. The R and BadVPN2 fields are not writable. The register contains the Virtual Pin Number of the most recently translated virtual address that was not validly translated. It contains bits 39.13 of the virtual address that caused the TLB miss. Bit 12 is excluded because a single TLB entry maps an even-odd page pair. The given format can be used directly as an address for pages of size 4KB. For all other page sizes this value must be shifted and masked.
The PErr register pertains little to the focus of the document, therefore it ain't worth a mention. The only possible point of interest is that the register is readable and writeable by software.
The CacheErr register is also about as relevant to the purpose of this doc as er.... a jellyfish?
The TagLo register is a 32-bit readable and writeable register. used to hold the cache tag during cache initialization and diagnostics, it is used to hold the cache tag. The two tag registers can be written by the CACHE and MTC0 instructions.
The ErrorEPC register is kinda alike to the EPC, but is used to store the PC upon Reset and Non Maskable Interrupt exceptions. It is both readable and writeable and contains the virtual address at which instruction processing can resume after an Error or Reset/NMI exceptions. The EPC register contains either the virtual address of the instruction (the direct cause of the exception), or (when that instruction is in a branch delay slot), the virtual address of the immediately preceding branch or jump instruction. There is no branch delay slot indication for ErrorEPC.
This doc will make a heck of a lot more sense once you see the full register tables. Their inclusion is a priority for our next update (perhaps!)
Part of the N64d compilation of Nintendo64 documents.
1997 Denary Notation
