N64d (v0.2) - Background information on the R4300i co-processor
Coprocessor 0 (CP0) Documentation
Compiled by Andy Simpson 1997
Source: (www.sgi.com)
Q: What does the CP0 do?
A: The CP0 performs two tasks; processor memory management and exception processing. It is separated into four units:
CP0reg (CP0 Register Files)
TLB (Translation Look-aside Buffer)
ITLB (Instruction TLB)
CP0ctl (CP0 Control Unit)
The CP0 registers consist of two sets of different function:
Set one contains registers that support the TLB operations
Set two is contains registers that reflect processor state.
All of the CP0 registers can be read by software. Software can write all registers except Random, BadVAddr, PrId, and MskId.
For more info on registers, see CP0reg.doc
Q: Okay. So what does each set do?
A: It works like this:-
The CP0ctl organisies data transfer to and from the TLB, CP0 and ITLB registers. The instruction decode signals are taken from the integer unit and interpreted, determining whether a to read or write a CP0 register. It generates control signals for reading and writing TLB and ITLB entries. Exception processing is also handled by the CP0ctl. The purpose here is to communicate with the pipeline control unit for interrupt signalling and notification of TLB exceptions. It also performs address checking regarding the type of instruction being executed and various state bits in the Status register.
The Translation Look-aside Buffers (micro-TLB and joint TLB) translate both instruction and data virtual addresses into physical addresses. Physical addresses are needed by the cache for tag checking, by the system interface for off-chip memory accessing and also by various CP0 registers. The jTLB translates the lower 40 bits of the 64-bit virtual address size defined in the MIPS-III architecture, and provides a 32-bit physical address.
The joint TLB contains 32 entries each simultaneously checked for a match with the extended virtual address. Each TLB entry maps an even-odd pair of pages. The page is either 4K, 16K, 64K, 256K, 1M, 4M or 16M bytes in size (specified on a per-entry basis by the MASK bit-mask field of the entry).
Direct quote from source: "A virtual address matches a TLB entry when the virtual page number (VPN) field of the virtual address equals the VPN field of the TLB entry, and either the Global (G) bit of the TLB entry is set or the address space identifier (ASID) field of the virtual address (as held in the EntryHi register) matches the ASID field of the TLB entry. Although the valid (V) bit of the entry must be set for a valid translation to take place, it is not involved in the determination of a matching TLB entry".
The operation of the TLB will not be defined if more than one entry in the TLB matches. If one matches, the physical address and access control bits (N, D, and V) are retrieved otherwise a TLB refill exception will occur. If the access control bits (D and V) indicate that the access is not valid, a TLB modification or TLB invalid exception will occur.
The R4300i also utilises a two entry micro-TLB. This dedicated to instruction address translation. This allows instruction address translation to be carried out at the same time as data address translation. If there is a miss in the micro-TLB, a stall will occur whilst the new TLB entry is transferred from the joint TLB to the micro-TLB. Each micro-TLB entry maps to a 4K byte page size only.
Part of the N64d compilation of Nintendo64 documents.
1997 Denary Notation
