Copy Link
Add to Bookmark
Report
Nintendo 64 Toolkit: opcodes v1.1
This is a collection of programming information for the Nintendo 64 that i've gathered. It is currently splitted into these parts:
n64ops#a.txt - Brief list of R4300i opcodes
n64ops#b.txt - Detailed list of R4300i opcodes
n64ops#c.txt - R4300i opcode matrix
n64ops#d.txt - Brief list of RSP opcodes
n64ops#e.txt - Detailed list of RSP opcodes
n64ops#f.txt - RSP opcode matrix
n64ops#g.txt - ROM header information
n64ops#h.txt - Nintendo 64 memory map
Contributed by other people:
rcp.txt - RCP information, opcodes etc.
sound.txt - How to play sound on the N64.
controll.txt - How to access the N64 controller.
If you find any errors in the text, or miss anything, please inform me about that, either by email <anarko@flashback.net> or ICQ #: 3299208.
/anarko
http://members.xoom.com/n64toolkit/ - Nintendo 64 Toolkit homepage.
Thank-you's to:
Niki W. Waibel - Additional controller information
Ben Stembridge - For his *great* support, many thanks!
Fractal - For some contry codes.
JL_Picard - For giving me some odd boot codes.
Michael Tedder - For Project UnReality and a link on my page.
Gordon Hollingworth - For his great support.
RenÈ - For help with some pseudo opcodes.
Zilmar - For everything you've done for me!
And very much thank you to all Nintendo 64 programmers out there,
keep on moohing!
Titanik - for the controller info.
Resources:
R4300i documentation from MIPS Technologies, Inc.
R4000 Instructions from Silicon Graphics
Project UnReality by Michael Tedder
#n64dev and #n64emu on EFnet.
Various emails and chats.
n64ops#a
Part A: Brief list of R4300i opcodes
****************************************************************************
** Explanations **
****************************************************************************
rs = 5-bit source register specifier
rt = 5-bit target (source/destination) register or branch condition
rd = 5-bit destination register specifier
sa = 5-bit shift amount
fs = 5-bit floating point source register specifier
ft = 5-bit floating point target (source/destination)
register or branch condition
fd = 5-bit floating point destination register specifier
base = 5-bit value
imm = 16 bit immediate value
offset = 16 bit branch displacement or address displacement
target = 26 bit jump target address
= Equal to > Greater than >= Greater than or equal to
<> Not equal to < Less than <= Less than or equal to
****************************************************************************
** Load and Store Instructions **
****************************************************************************
LB rt,offset(base) Load Byte
LBU rt,offset(base) Load Byte Unsigned
LD rt,offset(base) Load Doubleword
LDL rt,offset(base) Load Doubleword Left
LDR rt,offset(base) Load Doubleword Right
LH rt,offset(base) Load Halfword
LHU rt,offset(base) Load Halfword Unsigned
LL rt,offset(base) Load Linked word
LLD rt,offset(base) Load Linked Doubleword
LW rt,offset(base) Load Word
LWL rt,offset(base) Load Word Left
LWR rt,offset(base) Load Word Right
LWU rt,offset(base) Load Word Unsigned
SB rt,offset(base) Store Byte
SC rt,offset(base) Store Conditional word
SCD rt,offset(base) Store Conditional Doubleword
SD rt,offset(base) Store Doubleword
SDL rt,offset(base) Store Doubleword Left
SDR rt,offset(base) Store Doubleword Right
SH rt,offset(base) Store Halfword
SW rt,offset(base) Store Word
SWL rt,offset(base) Store Word Left
SWR rt,offset(base) Store Word Right
SYNC SYNChronize shared memory
****************************************************************************
** Atithmetic Instructions **
****************************************************************************
ADD rd,rs,rt ADD word
ADDI rt,rs,imm ADD Immediate word
ADDIU rt,rs,imm Add Immediate Unsigned word
ADDU rd,rs,rt Add Unsigned word
AND rd,rs,rt AND
ANDI rt,rs,imm AND Immediate
DADD rd,rs,rt Doubleword ADD
DADDI rt,rs,imm Doubleword ADD Immediate
DADDIU rt,rs,imm Doubleword ADD Immediate Unsigned
DADDU rd,rs,rt Doubleword ADD Unsigned
DDIV rs,rt Doubleword DIVide
DDIVU rs,rt Doubleword DIVide Unsigned
DIV rs,rt DIVide word
DIVU rs,rt DIVide Unsigned word
DMULT rs,rt Doubleword MULTiply
DMULTU rs,rt Doubleword MULTiply Unsigned
DSLL rd,rt,sa Doubleword Shift Left Logical
DSLL32 rd,rt,sa Doubleword Shift Left Logical +32
DSLLV rd,rt,rs Doubleword Shift Left Logical Variable
DSRA rd,rt,sa Doubleword Shift Right Arithmetic
DSRA32 rd,rt,sa Doubleword Shift Right Arithmetic +32
DSRAV rd,rt,rs Doubleword Shift Right Arithmetic Variable
DSRL rd,rt,sa Doubleword Shift Right Logical
DSRL32 rd,rt,sa Doubleword Shift Right Logical +32
DSRLV rd,rt,rs Doubleword Shift Right Logical Variable
DSUB rd,rs,rt Doubleword SUBtract
DSUBU rd,rs,rt Doubleword SUBtract Unsigned
LUI rt,imm Load Upper Immediate
MFHI rd Move From HI register
MFLO rd Move From LO register
MTHI rd Move To HI register
MTLO rd Move To LO register
MULT rs,rt MULTiply word
MULTU rs,rt MULTiply Unsigned word
NOR rd,rs,rt Not OR
OR rd,rs,rt OR
ORI rt,rs,imm OR Immediate
SLL rd,rt,sa Shift word Left Logical
SLLV rd,rt,rs Shift word Left Logical Variable
SLT rd,rs,rt Set on Less Than
SLTI rt,rs,imm Set on Less Than Immediate
SLTIU rt,rs,imm Set on Less Than Immediate Unsigned
SLTU rd,rs,rt Set on Less Than Unsigned
SRA rd,rt,sa Shift word Right Arithmetic
SRAV rd,rt,rs Shift word Right Arithmetic Variable
SRL rd,rt,sa Shift word Right Logical
SRLV rd,rt,rs Shift word Right Logical Variable
SUB rd,rs,rt SUBtract word
SUBU rd,rs,rt SUBtract Unsigned word
XOR rd,rs,rt eXclusive OR
XORI rt,rs,imm eXclusive OR Immediate
****************************************************************************
** Jump and Branch Instructions **
****************************************************************************
BEQ rs,rt,offset Branch on =
BEQL rs,rt,offset Branch on EQual Likely
BGEZ rs,offset Branch on >= Zero
BGEZAL rs,offset Branch on >= Zero And Link
BGEZALL rs,offset Branch on >= Zero And Link Likely
BGEZL rs,offset Branch on >= Equal to Zero Likely
BGTZ rs,offset Branch on > Zero
BGTZL rs,offset Branch on > Zero Likely
BLEZ rs,offset Branch on <= Equal to Zero
BLEZL rs,offset Branch on <= Zero Likely
BLTZ rs,offset Branch on < Zero
BLTZAL rs,offset Branch on < Zero And Link
BLTZALL rs,offset Branch on < Zero And Link Likely
BLTZL rs,offset Branch on < Zero Likely
BNE rs,rt,offset Branch on <>
BNEL rs,rt,offset Branch on <> Likely
J target Jump
JAL target Jump And Link
JALR rs,rd Jump And Link Register
JR rs Jump Register
****************************************************************************
** Special Instructions **
****************************************************************************
BREAK offset BREAKpoint
SYSCALL offset SYStem CALL
****************************************************************************
** Exception Instructions **
****************************************************************************
TEQ rs,rt Trap if =
TEQI rs,imm Trap if = Immediate
TGE rs,rt Trap if >=
TGEI rs,imm Trap if >= Immediate
TGEIU rs,imm Trap if >= Immediate Unsigned
TGEU rs,rt Trap if >= Unsigned
TLT rs,rt Trap if <
TLTI rs,imm Trap if < Immediate
TLTIU rs,imm Trap if < Immediate Unsigned
TLTU rs,rt Trap if < Unsigned
TNE rs,rt Trap if <>
TNEI rs,imm Trap if <> Immediate
****************************************************************************
** System Control Processor (COP0) Instructions **
****************************************************************************
CACHE op,offset(base) CACHE
ERET Return from Exception
MFC0 rt,fs Move Word From CP0
MTC0 rt,fs Move Word To CP0
TLBP Probe TLB for Matching Entry
TLBR Read Indexed TLB Entry
TLBWI Write Indexed TLB Entry
TLBWR Write Random TLB Entry
****************************************************************************
** Floating-point Unit, FPU (COP1) instructions **
****************************************************************************
ABS.fmt fd,fs floating-point ABSolute value
ADD.fmt fd,fs,ft floating-point ADD
BC1F offset Branch on FP False
BC1FL offset Branch on FP False Likely
BC1T offset Branch on FP True
BC1TL offset Branch on FP True Likely
C.cond.fmt fs,ft floating-point floating point Compare
CEIL.L.fmt fd,fs floating-point CEILing convert to Long fixed-point
CEIL.W.fmt fd,fs floating-point CEILing convert to Word fixed-point
CFC1 rt,fs Move control word From Floating-Point
CTC1 rt,fs Move control word To Floating-Point
CVT.D.fmt fd,fs floating-point ConVerT to Double floating-point
CVT.L.fmt fd,fs floating-point ConVerT to Long fixed-point
CVT.S.fmt fd,fs floating-point ConVerT to Single floating-point
CVT.W.fmt fd,fs floating-point ConVerT to Word fixed-point
DIV.fmt fd,fs,ft floating-point DIVide
DMFC1 rt,fs Doubleword Move From Floating-Point
DMTC1 rt,fs Doubleword Move To Floating-Point
FLOOR.L.fmt fd,fs floating-point FLOOR convert to Long fixed-point
FLOOR.W.fmt fd,fs floating-point FLOOR convert to Word fixed-point
LDC1 ft,offset(base) Load Doubleword to Floating-Point
LWC1 ft,offset(base) Load Word to Floating-Point
MFC1 rt,fs Move Word From Floating-Point
MOV.fmt fd,fs floating-point MOVe
MTC1 rt,fs Move Word To Floating-Point
MUL.fmt fd,fs,ft floating-point MULtiply
NEG.fmt fd,fs floating-point NEGate
ROUND.L.fmt fd,fs floating-point ROUND to Long fixed-point
ROUND.W.fmt fd,fs floating-point ROUND to Word fixed-point
SDC1 ft,offset(base) Store Doubleword from Floating-Point
SQRT.fmt fd,fs floating-point SQuare RooT
SUB.fmt fd,fs,ft floating-point SUBtract
SWC1 ft,offset(base) Store Word from Floating-Point
TRUNC.L.fmt fd,fs floating-point TRUNCate to Long fixed-point
TRUNC.W.fmt fd,fs floating-point TRUNCate to Word fixed-point
****************************************************************************
** Pseudo opcodes **
****************************************************************************
NOP Assembles to SLL r0, r0, 0
MOVE rd, rs Assembles to ADD rd, r0, rs
NEG rd, rt Assembles to SUB rd, r0, rt
NEGU rd, rs Assembles to SUBU rd, r0, rs
BNEZ rs, offset Assembles to BNE rs, r0, offset
BNEZL rs, offset Assembles to BNEL rs, r0, offset
BEQZ rs, offset Assembles to BEQ rs, r0, offset
BEQZL rs, offset Assembles to BEQL rs, r0, offset
B offset Assembles to BEQ r0, r0, offset
BAL offset Assembles to BGEZAL r0, offset
LI rt, imm Assembles to ORI rt, r0, imm (if imm is 16 bit)
or ADDIU rt, r0, imm
or LUI rt, high_16
ORI rt, rt, low_16 (if imm is 32 bit)
S.S ft, offset(base) Assembles to SWC1 ft, offset(base)
L.S ft, offset(base) Assembles to LWC1 ft, offset(base)
n64ops#b
Part B: Detailed list of R4300i opcodes
****************************************************************************
** Registers **
****************************************************************************
Main CPU registers:
-------------------
00h = r0/reg0 08h = t0/reg8 10h = s0/reg16 18h = t8/reg24
01h = at/reg1 09h = t1/reg9 11h = s1/reg17 19h = t9/reg25
02h = v0/reg2 0Ah = t2/reg10 12h = s2/reg18 1Ah = k0/reg26
03h = v1/reg3 0Bh = t3/reg11 13h = s3/reg19 1Bh = k1/reg27
04h = a0/reg4 0Ch = t4/reg12 14h = s4/reg20 1Ch = gp/reg28
05h = a1/reg5 0Dh = t5/reg13 15h = s5/reg21 1Dh = sp/reg29
06h = a2/reg6 0Eh = t6/reg14 16h = s6/reg22 1Eh = s8/reg30
07h = a3/reg7 0Fh = t7/reg15 17h = s7/reg23 1Fh = ra/reg31
COP0 registers:
---------------
00h = Index 08h = BadVAddr 10h = Config 18h = *RESERVED*
01h = Random 09h = Count 11h = LLAddr 19h = *RESERVED*
02h = EntryLo0 0Ah = EntryHi 12h = WatchLo 1Ah = PErr
03h = EntryLo1 0Bh = Compare 13h = WatchHi 1Bh = CacheErr
04h = Context 0Ch = Status 14h = XContext 1Ch = TagLo
05h = PageMask 0Dh = Cause 15h = *RESERVED* 1Dh = TagHi
06h = Wired 0Eh = EPC 16h = *RESERVED* 1Eh = ErrorEPC
07h = *RESERVED* 0Fh = PRevID 17h = *RESERVED* 1Fh = *RESERVED*
****************************************************************************
** Load and Store Instructions **
****************************************************************************
-----------------------------------------------------------------
| LB | Load Byte |
|-----------|---------------------------------------------------|
|100000 (32)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LB rt, offset(base)
Purpose: To load a byte from memory as a signed value.
Descrip: rt = byte[base+offset]
-----------------------------------------------------------------
| LBU | Load Byte Unsigned |
|-----------|---------------------------------------------------|
|100100 (36)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LBU rt, offset(base)
Purpose: To load a byte from memory as an unsigned value.
Descrip: rt = byte[base+offset]
-----------------------------------------------------------------
| LD | Load Doubleword |
|-----------|---------------------------------------------------|
|110111 (55)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LD rt, offset(base)
Purpose: To load a doubleword from memory.
Descrip: rt = doubleword[base+offset]
-----------------------------------------------------------------
| LDL | Load Doubleword Left |
|-----------|---------------------------------------------------|
|011010 (26)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LDL rt, offset(base)
Purpose: To load the most-significant part of a doubleword from
an unaligned memory address.
Descrip: left(rt) = right[base+offset]
-----------------------------------------------------------------
| LDR | Load Doubleword Right |
|-----------|---------------------------------------------------|
|011011 (27)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LDR rt, offset(base)
Purpose: To load the least-significant part of a doubleword from
an unaligned memory address.
Descrip: right(rt) = left[base+offset]
-----------------------------------------------------------------
| LH | Load Halfword |
|-----------|---------------------------------------------------|
|100001 (33)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LH rt, offset(base)
Purpose: To load a halfword from memory as a signed value.
Descrip: rt = halfword[base+offset]
-----------------------------------------------------------------
| LHU | Load Halfword Unsigned |
|-----------|---------------------------------------------------|
|100101 (37)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LHU rt, offset(base)
Purpose: To load a halfword from memory as an unsigned value.
Descrip: rt = halfword[base+offset]
-----------------------------------------------------------------
| LL | Load Linked Word |
|-----------|---------------------------------------------------|
|110000 (48)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LL rt, offset(base)
Purpose: To load a word from memory for an atomic read-modify-write.
-----------------------------------------------------------------
| LLD | Load Linked Doubleword |
|-----------|---------------------------------------------------|
|110100 (52)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LLD rt, offset(base)
Purpose: To load a doubleword from memory for an atomic read-modify-write.
-----------------------------------------------------------------
| LW | Load Word |
|-----------|---------------------------------------------------|
|100011 (35)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LW rt, offset(base)
Purpose: To load a word from memory as a signed value.
Descrip: rt = word[base+offset]
-----------------------------------------------------------------
| LWL | Load Word Left |
|-----------|---------------------------------------------------|
|100010 (34)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LWL rt, offset(base)
Purpose: To load the most-significant part of a word as a
signed value from an unaligned memory address.
Descrip: left(rt) = right[base+offset]
-----------------------------------------------------------------
| LWR | Load Word Right |
|-----------|---------------------------------------------------|
|100110 (38)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LWR rt, offset(base)
Purpose: To load the least-significant part of a word from an
unaligned memory address as a signed value.
Descrip: right(rt) = left[base+offset]
-----------------------------------------------------------------
| LWU | Load Word Unsigned |
|-----------|---------------------------------------------------|
|100111 (39)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: LWU rt, offset(base)
Purpose: To load a word from memory as an unsigned value.
Descrip: rt = word[base+offset]
-----------------------------------------------------------------
| SB | Store Byte |
|-----------|---------------------------------------------------|
|101000 (40)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SB rt, offset(base)
Purpose: To store a byte to memory.
Descrip: byte[base+offset] = rt
-----------------------------------------------------------------
| SC | Store Conditional Word |
|-----------|---------------------------------------------------|
|111000 (56)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SC rt, offset(base)
Purpose: To store a word to memory to complete an atomic read-modify-write.
-----------------------------------------------------------------
| SCD | Store Conditional Doubleword |
|-----------|---------------------------------------------------|
|111100 (60)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SCD rt, offset(base)
Purpose: To store a doubleword to memory to complete an atomic
read-modify-write.
-----------------------------------------------------------------
| SD | Store Doubleword |
|-----------|---------------------------------------------------|
|111111 (63)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SD rt, offset(base)
Purpose: To store a doubleword to memory.
Descrip: doulbeword[base+offset] = rt
-----------------------------------------------------------------
| SDL | Store Doubleword Left |
|-----------|---------------------------------------------------|
|101100 (44)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SDL rt, offset(base)
Purpose: To store the most-significant part of a doubleword to
an unaligned memory address.
Descrip: right[base+offset] = left(rt)
-----------------------------------------------------------------
| SDR | Store Doubleword Right |
|-----------|---------------------------------------------------|
|101101 (45)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SDR rt, offset(base)
Purpose: To store the least-significant part of a doubleword to
an unaligned memory address.
Descrip: left[base+offset] = right(rt)
-----------------------------------------------------------------
| SH | Store Halfword |
|-----------|---------------------------------------------------|
|101001 (41)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SH rt, offset(base)
Purpose: To store a halfword to memory.
Descrip: halfword[base+offset] = rt
-----------------------------------------------------------------
| SW | Store Word |
|-----------|---------------------------------------------------|
|101011 (43)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SW rt, offset(base)
Purpose: To store a word to memory.
Descrip: word[base+offset] = rt
-----------------------------------------------------------------
| SWL | Store Word Left |
|-----------|---------------------------------------------------|
|101010 (42)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SWL rt, offset(base)
Purpose: To store the most-significant part of a word to an
unaligned memory address.
Descrip: right[base+offset] = left(rt)
-----------------------------------------------------------------
| SWR | Store Word Right |
|-----------|---------------------------------------------------|
|101110 (46)| base | rt | offset |
------6----------5---------5-------------------16----------------
Format: SWR rt, offset(base)
Purpose: To store the least-significant part of a word to an
unaligned memory address.
Descrip: left[base+offset] = right(rt)
-----------------------------------------------------------------
| SYNC | SYNChronize shared memory |
|-----------|---------------------------------------------------|
| 000000 | 0000 0000 0000 000 | stype |001111 (15)|
------6-------------------15-------------------5---------6-------
Format: SYNC (stype = 0 implied)
Purpose: To order loads and stores to shared memory in a
multiprocessor system.
****************************************************************************
** Atithmetic Instructions **
****************************************************************************
-----------------------------------------------------------------
| ADD | ADD word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100000 (32)|
------6----------5---------5---------5---------5----------6------
Format: ADD rd, rs, rt
Purpose: To add 32-bit integers. If overflow occurs, then trap.
Comment: ADD rd, r0, rs is equal to a MOVE rd, rs
Descrip: rd = rs + rt
-----------------------------------------------------------------
| ADDI | ADD Immediate word |
|-----------|---------------------------------------------------|
|001000 (8) | rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ADDI rt, rs, immediate
Purpose: To add a constant to a 32-bit integer.
If overflow occurs, then trap.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| ADDIU | ADD Immediate Unsigned word |
|-----------|---------------------------------------------------|
|001001 (9) | rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ADDIU rt, rs, immediate
Purpose: To add a constant to a 32-bit integer.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| ADDU | ADD Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100001 (33)|
------6----------5---------5---------5---------5----------6------
Format: ADDU rd, rs, rt
Purpose: To add 32-bit integers.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| AND | AND |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100100 (36)|
------6----------5---------5---------5---------5----------6------
Format: AND rd, rs, rt
Purpose: To do a bitwise logical AND.
Descrip: rd = (rs AND rt)
-----------------------------------------------------------------
| ANDI | AND Immediate |
|-----------|---------------------------------------------------|
|001100 (12)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ANDI rt, rs, immediate
Purpose: To do a bitwise logical AND with a constant.
Descrip: rt = (rs AND immediate)
-----------------------------------------------------------------
| DADD | Doubleword ADD |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101100 (44)|
------6----------5---------5---------5---------5----------6------
Format: DADD rd, rs, rt
Purpose: To add 64-bit integers. If overflow occurs, then trap.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| DADDI | Doubleword ADD Immediate |
|-----------|---------------------------------------------------|
|011000 (24)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: DADDI rt, rs, immediate
Purpose: To add a constant to a 64-bit integer.
If overflow occurs, then trap.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| DADDIU | Doubleword ADD Immediate Unsigned |
|-----------|---------------------------------------------------|
|011001 (25)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: DADDIU rt, rs, immediate
Purpose: To add a constant to a 64-bit integer.
Descrip: rt = rs + immediate
-----------------------------------------------------------------
| DADDU | Doubleword ADD Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101101 (45)|
------6----------5---------5---------5---------5----------6------
Format: DADDU rd, rs, rt
Purpose: To add 64-bit integers.
Descrip: rd = rs + rt
-----------------------------------------------------------------
| DDIV | Doubleword DIVide |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011110 (30)|
------6----------5---------5--------------10--------------6------
Format: DDIV rs, rt
Purpose: To divide 64-bit signed integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DDIVU | Doubleword DIVide Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011111 (31)|
------6----------5---------5--------------10--------------6------
Format: DDIVU rs, rt
Purpose: To divide 64-bit unsigned integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DIV | DIVide word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011010 (26)|
------6----------5---------5--------------10--------------6------
Format: DIV rs, rt
Purpose: To divide 32-bit signed integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DIVU | DIVide Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011011 (27)|
------6----------5---------5--------------10--------------6------
Format: DIVU rs, rt
Purpose: To divide 32-bit unsigned integers.
Descrip: LO = rs / rt; HI = rs MOD rt
-----------------------------------------------------------------
| DMULT | Doubleword MULTiply |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011100 (28)|
------6----------5---------5--------------10--------------6------
Format: DMULT rs, rt
Purpose: To multiply 64-bit signed integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| DMULTU | Doubleword MULTiply Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011101 (29)|
------6----------5---------5--------------10--------------6------
Format: DMULTU rs, rt
Purpose: To multiply 64-bit unsigned integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| DSLL | Doubleword Shift Left Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111000 (56)|
------6----------5---------5---------5---------5----------6------
Format: DSLL rd, rt, sa
Purpose: To left shift a doubleword by a fixed amount -- 0 to 31 bits.
Descrip: rd = rt << sa
-----------------------------------------------------------------
| DSLL32 | Doubleword Shift Left Logical +32 |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111100 (60)|
------6----------5---------5---------5---------5----------6------
Format: DSLL32 rd, rt, sa
Purpose: To left shift a doubleword by a fixed amount -- 32 to 63 bits.
Descrip: rd = rt << (sa+32)
-----------------------------------------------------------------
| DSLLV | Doubleword Shift Left Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |010100 (20)|
------6----------5---------5---------5---------5----------6------
Format: DSLLV rd, rt, rs
Purpose: To left shift a doubleword by a variable number of bits.
Descrip: rd = rt << rs
-----------------------------------------------------------------
| DSRA | Doubleword Shift Right Arithmetic |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111011 (59)|
------6----------5---------5---------5---------5----------6------
Format: DSRA rd, rt, sa
Purpose: To arithmetic right shift a doubleword by a fixed
amount -- 0 to 31 bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| DSRA32 | Doubleword Shift Right Arithmetic +32 |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111111 (63)|
------6----------5---------5---------5---------5----------6------
Format: DSRA32 rd, rt, sa
Purpose: To arithmetic right shift a doubleword by a fixed
amount -- 32-63 bits.
Descrip: rd = rt >> (sa+32)
-----------------------------------------------------------------
| DSRAV | Doubleword Shift Right Arithmetic Variable |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | rs |010111 (23)|
------6----------5---------5---------5---------5----------6------
Format: DSRAV rd, rt, rs
Purpose: To arithmetic right shift a doubleword by a variable
number of bits.
Descrip: rd = rt >> rs
-----------------------------------------------------------------
| DSRL | Doubleword Shift Right Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111010 (58)|
------6----------5---------5---------5---------5----------6------
Format: DSRL rd, rt, sa
Purpose: To logical right shift a doubleword by a fixed amount
-- 0 to 31 bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| DSRL32 | Doubleword Shift Right Logical +32 |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |111110 (62)|
------6----------5---------5---------5---------5----------6------
Format: DSRL32 rd, rt, sa
Purpose: To logical right shift a doubleword by a fixed amount
-- 32 to 63 bits.
Descrip: rd = rt >> (sa+32)
-----------------------------------------------------------------
| DSRLV | Doubleword Shift Right Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | rs |010110 (22)|
------6----------5---------5---------5---------5----------6------
Format: DSRLV rd, rt, rs
Purpose: To logical right shift a doubleword by a variable number of bits.
Descrip: rd = rt >> rs
-----------------------------------------------------------------
| DSUB | Doubleword SUBtract |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101110 (46)|
------6----------5---------5---------5---------5----------6------
Format: DSUB rd, rs, rt
Purpose: To subtract 64-bit integers; trap if overflow.
Descrip: rd = rs - rt
-----------------------------------------------------------------
| DSUBU | Doubleword SUBtract Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101111 (47)|
------6----------5---------5---------5---------5----------6------
Format: DSUBU rd, rs, rt
Purpose: To subtract 64-bit integers.
Descrip: rd = rs - rt
-----------------------------------------------------------------
| LUI | Load Upper Immediate |
|-----------|---------------------------------------------------|
|001111 (15)| 00000 | rt | immediate |
------6----------5---------5-------------------16----------------
Format: LUI rt, immediate
Purpose: To load a constant into the upper half of a word.
Descrip: rt = immediate * 10000h
-----------------------------------------------------------------
| MFHI | Move From HI register |
|-----------|---------------------------------------------------|
| 000000 | 0000 0000 00 | rd | 00000 |010000 (16)|
------6---------------10-------------5---------5----------6------
Format: MFHI rd
Purpose: To copy the special purpose HI register to a GPR.
Descrip: rd = HI
-----------------------------------------------------------------
| MFLO | Move From LO register |
|-----------|---------------------------------------------------|
| 000000 | 0000 0000 00 | rd | 00000 |010010 (18)|
------6---------------10-------------5---------5----------6------
Format: MFLO rd
Purpose: To copy the special purpose LO register to a GPR.
Descrip: rd = LO
-----------------------------------------------------------------
| MTHI | Move To HI register |
|-----------|---------------------------------------------------|
| 000000 | rs | 0000 0000 0000 000 |010001 (17)|
------6----------5------------------15--------------------6------
Format: MTHI rs
Purpose: To copy a GPR to the special purpose HI register.
-----------------------------------------------------------------
| MTLO | Move To LO register |
|-----------|---------------------------------------------------|
| 000000 | rs | 0000 0000 0000 000 |010011 (19)|
------6----------5------------------15--------------------6------
Format: MTLO rs
Purpose: To copy a GPR to the special purpose LO register.
-----------------------------------------------------------------
| MULT | MULTiply word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011000 (24)|
------6----------5---------5--------------10--------------6------
Format: MULT rs, rt
Purpose: To multiply 32-bit signed integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| MULTU | MULTiply Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | 0000 0000 00 |011001 (25)|
------6----------5---------5--------------10--------------6------
Format: MULTU rs, rt
Purpose: To multiply 32-bit unsigned integers.
Descrip: LO = low(rs*rt); HI = high(rs*rt)
-----------------------------------------------------------------
| NOR | Not OR |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100111 (39)|
------6----------5---------5---------5---------5----------6------
Format: NOR rd, rs, rt
Purpose: To do a bitwise logical NOT OR.
Descrip: rd = (rs NOR rt)
-----------------------------------------------------------------
| OR | OR |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100101 (37)|
------6----------5---------5---------5---------5----------6------
Format: OR rd, rs, rt
Purpose: To do a bitwise logical OR.
Descrip: rd = (rs OR rt)
-----------------------------------------------------------------
| ORI | OR Immediate |
|-----------|---------------------------------------------------|
|001101 (13)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: ORI rt, rs, immediate
Purpose: To do a bitwise logical OR with a constant.
Comment: ORI rt, r0, imm is equal to a LI rt, imm
Descrip: rt = (rs OR immediate)
-----------------------------------------------------------------
| SLL | Shift word Left Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |000000 (0) |
------6----------5---------5---------5---------5----------6------
Format: SLL rd, rt, sa
Purpose: To left shift a word by a fixed number of bits.
Comment: SLL r0, r0, 0 is equal to a NOP (No OPeration)
Descrip: rd = rt << sa
-----------------------------------------------------------------
| SLLV | Shift word Left Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |000100 (4) |
------6----------5---------5---------5---------5----------6------
Format: SLLV rd, rt, rs
Purpose: To left shift a word by a variable number of bits.
Descrip: rd = rt << sa
-----------------------------------------------------------------
| SLT | Set on Less Than |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101010 (42)|
------6----------5---------5---------5---------5----------6------
Format: SLT rd, rs, rt
Purpose: To record the result of a less-than comparison.
Descrip: if rs < rt then rd = 1 else rd = 0
-----------------------------------------------------------------
| SLTI | Set on Less Than Immediate |
|-----------|---------------------------------------------------|
|001010 (10)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: SLTI rt, rs, immediate
Purpose: To record the result of a less-than comparison with a constant.
Descrip: if rs < immediate then rd = 1 else rd = 0
-----------------------------------------------------------------
| SLTIU | Set on Less Than Immediate Unsigned |
|-----------|---------------------------------------------------|
|001011 (11)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: SLTIU rt, rs, immediate
Purpose: To record the result of an unsigned less-than
comparison with a constant.
Descrip: if rs < immediate then rd = 1 else rd = 0
-----------------------------------------------------------------
| SLTU | Set on Less Than Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |101011 (43)|
------6----------5---------5---------5---------5----------6------
Format: SLTU rd, rs, rt
Purpose: To record the result of an unsigned less-than comparison.
Descrip: if rs < rt then rd = 1 else rd = 0
-----------------------------------------------------------------
| SRA | Shift word Right Arithmetic |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |000011 (3) |
------6----------5---------5---------5---------5----------6------
Format: SRA rd, rt, sa
Purpose: To arithmetic right shift a word by a fixed number of bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| SRAV | Shift word Right Arithmetic Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |000111 (7) |
------6----------5---------5---------5---------5----------6------
Format: SRAV rd, rt, rs
Purpose: To arithmetic right shift a word by a variable number of bits.
Descrip: rd = rt >> rs
-----------------------------------------------------------------
| SRL | Shift word Right Logical |
|-----------|---------------------------------------------------|
| 000000 | 00000 | rt | rd | sa |000010 (2) |
------6----------5---------5---------5---------5----------6------
Format: SRL rd, rt, sa
Purpose: To logical right shift a word by a fixed number of bits.
Descrip: rd = rt >> sa
-----------------------------------------------------------------
| SRLV | Shift word Right Logical Variable |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |000110 (6) |
------6----------5---------5---------5---------5----------6------
Format: SRLV rd, rt, rs
Purpose: To logical right shift a word by a variable number of bits.
Descrip: rd = rt >> rs
-----------------------------------------------------------------
| SUB | SUBtract word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100010 (34)|
------6----------5---------5---------5---------5----------6------
Format: SUB rd, rs, rt
Purpose: To subtract 32-bit integers. If overflow occurs, then trap.
Comment: SUB rd, r0, rt is equal to a NEG rd, rt
Descrip: rd = rs - rt
-----------------------------------------------------------------
| SUBU | SUBtract Unsigned word |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100011 (35)|
------6----------5---------5---------5---------5----------6------
Format: SUBU rd, rs, rt
Purpose: To subtract 32-bit integers. No trap on overflow.
Comment: SUBU rd, r0, rs is equal to a NEGU rd, rs
Descrip: rd = rs - rt
-----------------------------------------------------------------
| XOR | eXclusive OR |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | rd | 00000 |100110 (38)|
------6----------5---------5---------5---------5----------6------
Format: XOR rd, rs, rt
Purpose: To do a bitwise logical EXCLUSIVE OR.
Descrip: rd = (rs XOR rt)
-----------------------------------------------------------------
| XORI | eXclusive OR Immediate |
|-----------|---------------------------------------------------|
|001110 (14)| rs | rt | immediate |
------6----------5---------5-------------------16----------------
Format: XORI rt, rs, immediate
Purpose: To do a bitwise logical EXCLUSIVE OR with a constant.
Descrip: rd = (rs XOR immediate)
****************************************************************************
** Jump and Branch Instructions **
****************************************************************************
-----------------------------------------------------------------
| BEQ | Branch on EQual |
|-----------|---------------------------------------------------|
|000100 (4) | rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BEQ rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch.
Comment: BEQ rs, r0, offset is equal to a BEQZ rs, offset
BEQ r0, r0, offset is equal to a B offset
Descrip: branch if rs = rt
-----------------------------------------------------------------
| BEQL | Branch on EQual Likley |
|-----------|---------------------------------------------------|
|010100 (20)| rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BEQL rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Comment: BEQL rs, r0, offset is equal to a BEQZL rs, offset
Descrip: branch if rs = rt
-----------------------------------------------------------------
| BGEZ | Branch on Greater than or Equal to Zero |
|-----------|---------------------------------------------------|
| 000001 | rs |00001 (1)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs >= 0 (signed)
-----------------------------------------------------------------
| BGEZAL | Branch on Greater than or Equal to Zero And Link |
|-----------|---------------------------------------------------|
| 000001 | rs |10001(17)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZAL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure call.
Comment: BGEZAL r0, offset is equal to a BAL offset
Descrip: branch if rs >= 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BGEZALL | Branch on Greater than or Equal to Zero And Link Likley
|-----------|---------------------------------------------------|
| 000001 | rs |10011(19)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZALL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure call;
execute the delay slot only if the branch is taken.
Descrip: branch if rs >= 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BGEZL | Branch on Greater than or Equal to Zero Likley |
|-----------|---------------------------------------------------|
| 000001 | rs |00011 (3)| offset |
------6----------5---------5-------------------16----------------
Format: BGEZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs >= 0 (signed)
-----------------------------------------------------------------
| BGTZ | Branch on Greater than Zero |
|-----------|---------------------------------------------------|
|000111 (7) | rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BGTZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs > 0 (signed)
-----------------------------------------------------------------
| BGTZL | Branch on Greater Than Zero Likley |
|-----------|---------------------------------------------------|
|010111 (23)| rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BGTZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs > 0 (signed)
-----------------------------------------------------------------
| BLEZ | Branch on Less than or Equal to Zero |
|-----------|---------------------------------------------------|
|000110 (6) | rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BLEZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs <= 0 (signed)
-----------------------------------------------------------------
| BLEZL | Branch on Less than or Equal to Zero Likley |
|-----------|---------------------------------------------------|
|010110 (22)| rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BLEZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs <= 0 (signed)
-----------------------------------------------------------------
| BLTZ | Branch on Less Than Zero |
|-----------|---------------------------------------------------|
| 000001 | rs | 00000 | offset |
------6----------5---------5-------------------16----------------
Format: BLTZ rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch.
Descrip: branch if rs < 0 (signed)
-----------------------------------------------------------------
| BLTZAL | Branch on Less Than Zero And Link |
|-----------|---------------------------------------------------|
| 000001 | rs | 10000 | offset |
------6----------5---------5-------------------16----------------
Format: BLTZAL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure call.
Descrip: branch if rs < 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BLTZALL | Branch on Less Than Zero And Link Likley |
|-----------|---------------------------------------------------|
| 000001 | rs | 10010 | offset |
------6----------5---------5-------------------16----------------
Format: BLTZALL rs, offset
Purpose: To test a GPR then do a PC-relative conditional procedure
call; execute the delay slot only if the branch is taken.
Descrip: branch if rs < 0 (signed) (return address in ra)
-----------------------------------------------------------------
| BLTZL | Branch on Less Than Zero Likley |
|-----------|---------------------------------------------------|
| 000001 | rs |00010 (2)| offset |
------6----------5---------5-------------------16----------------
Format: BLTZL rs, offset
Purpose: To test a GPR then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Descrip: branch if rs < 0 (signed)
-----------------------------------------------------------------
| BNE | Branch on Not Equal |
|-----------|---------------------------------------------------|
|000101 (5) | rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BNE rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch.
Comment: BNE rs, r0, offset is equal to a BNEZ rs, offset
Descrip: branch if rs <> rt
-----------------------------------------------------------------
| BNEL | Branch on Not Equal Likley |
|-----------|---------------------------------------------------|
|010101 (21)| rs | rt | offset |
------6----------5---------5-------------------16----------------
Format: BNEL rs, rt, offset
Purpose: To compare GPRs then do a PC-relative conditional branch;
execute the delay slot only if the branch is taken.
Comment: BNEL rs, r0, offset is equal to a BNEZL rs, offset
Descrip: branch if rs <> rt
-----------------------------------------------------------------
| J | Jump |
|-----------|---------------------------------------------------|
|000010 (2) | instr_index |
------6-------------------------------26-------------------------
Format: J target
Purpose: To branch within the current 256 MB aligned region.
-----------------------------------------------------------------
| JAL | Jump And Link |
|-----------|---------------------------------------------------|
|000011 (3) | instr_index |
------6-------------------------------26-------------------------
Format: JAL target
Purpose: To procedure call within the current 256 MB aligned region.
Descrip: return address in ra
-----------------------------------------------------------------
| JALR | Jump And Link Register |
|-----------|---------------------------------------------------|
| 000000 | rs | 00000 | rd | 00000 |001001 (9) |
------6----------5---------5---------5---------5----------6------
Format: JALR rs, rd
Purpose: To procedure call to an instruction address in a register.
Descrip: return address in rd
-----------------------------------------------------------------
| JR | Jump Register |
|-----------|---------------------------------------------------|
| 000000 | rs | 0000 0000 0000 000 |001000 (8) |
------6----------5------------------15--------------------6------
Format: JR rs
Purpose: To branch to an instruction address in a register.
Descrip: PC = rs
****************************************************************************
** Special instructions **
****************************************************************************
-----------------------------------------------------------------
| BREAK | BREAKpoint |
|-----------|---------------------------------------------------|
| 000000 | code |001101 (13)|
------6--------------------------20-----------------------6------
Format: BREAK offset
Purpose: To cause a Breakpoint exception.
-----------------------------------------------------------------
| SYSCALL | SYStem CALL |
|-----------|---------------------------------------------------|
| 000000 | code |001100 (12)|
------6--------------------------20-----------------------6------
Format: SYSCALL offset
Purpose: To cause a System Call exception.
****************************************************************************
** Exception Instructions **
****************************************************************************
-----------------------------------------------------------------
| TEQ | Trap if EQual |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110100 (52)|
------6----------5---------5--------------10--------------6------
Format: TEQ rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs = rt then trap
-----------------------------------------------------------------
| TEQI | Trap if EQual Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01100(12)| immediate |
------6----------5---------5-------------------16----------------
Format: TEQI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs = immediate then trap
-----------------------------------------------------------------
| TGE | Trap if Greater or Equal |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110000 (48)|
------6----------5---------5--------------10--------------6------
Format: TGE rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs >= rt then trap
-----------------------------------------------------------------
| TGEI | Trap if Greater or Equal Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01000 (8)| immediate |
------6----------5---------5-------------------16----------------
Format: TGEI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs >= immediate then trap
-----------------------------------------------------------------
| TGEIU | Trap if Greater or Equal Immediate Unsigned |
|-----------|---------------------------------------------------|
| 000001 | rs |01001 (9)| immediate |
------6----------5---------5-------------------16----------------
Format: TGEIU rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs >= immediate then trap
-----------------------------------------------------------------
| TGEU | Trap if Greater or Equal Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110001 (49)|
------6----------5---------5--------------10--------------6------
Format: TGEU rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs >= rt then trap
-----------------------------------------------------------------
| TLT | Trap if Less Than |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110010 (50)|
------6----------5---------5--------------10--------------6------
Format: TLT rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs < rt then trap
-----------------------------------------------------------------
| TLTI | Trap if Less Than Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01010(10)| immediate |
------6----------5---------5-------------------16----------------
Format: TLTI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs < immediate then trap (signed)
-----------------------------------------------------------------
| TLTIU | Trap if Less Than Immediate Unsigned |
|-----------|---------------------------------------------------|
| 000001 | rs |01011(11)| immediate |
------6----------5---------5-------------------16----------------
Format: TLTIU rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs < immediate then trap
-----------------------------------------------------------------
| TLTU | Trap if Less Than Unsigned |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110011 (51)|
------6----------5---------5--------------10--------------6------
Format: TLTU rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs < rt then trap
-----------------------------------------------------------------
| TNE | Trap if Not Equal |
|-----------|---------------------------------------------------|
| 000000 | rs | rt | code |110110 (54)|
------6----------5---------5--------------10--------------6------
Format: TNE rs, rt
Purpose: To compare GPRs and do a conditional Trap.
Descrip: if rs <> rt then trap
-----------------------------------------------------------------
| TNEI | Trap if Not Equal Immediate |
|-----------|---------------------------------------------------|
| 000001 | rs |01110(14)| immediate |
------6----------5---------5-------------------16----------------
Format: TNEI rs, immediate
Purpose: To compare a GPR to a constant and do a conditional Trap.
Descrip: if rs <> immediate then trap
****************************************************************************
** System Control Processor (COP0) Instructions **
****************************************************************************
-----------------------------------------------------------------
| CACHE | CACHE |
|-----------|---------------------------------------------------|
|101111 (47)| base | op | offset |
------6----------5---------5-------------------16----------------
Format: CACHE op, offset(base)
Purpose: The 16-bit offset is sign-extended and added to the contents of
general register base to form a virtual address. The virtual
address is translated to a physical address using the TLB, and the
5-bit sub-opcode specifies a cache operation for that address.
-----------------------------------------------------------------
| ERET | Return from Exception |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 |011000 (24)|
------6------1-------------------19-----------------------6------
Format: ERET
Purpose: ERET is the R4300 instruction for returning from an interrupt,
exception, or error trap. Unlike a branch or jump instruction,
ERET does not execute the next instruction.
-----------------------------------------------------------------
| MFC0 | Move word From CP0 |
|-----------|---------------------------------------------------|
| 010000 |00000 (0)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MFC0 rt, rd
Purpose: To copy a word from an FPR to a GPR.
Descrip: rt = COP rd
-----------------------------------------------------------------
| MTC0 | Move word to CP0 |
|-----------|---------------------------------------------------|
| 010000 |00100 (4)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MTC0 rt, rd
Purpose: To copy a word from a GPR to an FPR.
Descrip: COP rd = rt
-----------------------------------------------------------------
| TLBP | Translation Lookaside Buffer Probe |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 001000 (8)|
------6------1-------------------19-----------------------6------
Format: TLBP
Purpose: The Index register is loaded with the address of the TLB entry
whose contents match the contents of the EntryHi register. If no
TLB entry matches, the high-order bit of the Index register is set.
The architecture does not specify the operation of memory references
associated with the instruction immediately after a TLBP instruction,
nor is the operation specified if more than one TLB entry matches.
-----------------------------------------------------------------
| TLBR | Translation Lookaside Buffer Read |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 000001 (1)|
------6------1-------------------19-----------------------6------
Format: TLBR
Purpose: The G bit (which controls ASID matching) read from the TLB is
written into both of the EntryLo0 and EntryLo1 registers.
The EntryHi and EntryLo registers are loaded with the contents of
the TLB entry pointed at by the contents of the TLB Index register.
The operation is invalid (and the results are unspecified) if the
contents of the TLB Index register are greater than the number of
TLB entries in the processor.
-----------------------------------------------------------------
| TLBWI | Translation Lookaside Buffer Write Index |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 000010 (2)|
------6------1-------------------19-----------------------6------
Format: TLBWI
Purpose: The G bit of the TLB is written with the logical AND of the G bits
in the EntryLo0 and EntryLo1 registers. The TLB entry pointed at by
the contents of the TLB Index register is loaded with the contents
of the EntryHi and EntryLo registers. The operation is invalid (and
the results are unspecified) if the contents of the TLB Index
register are greater than the number of TLB entries in the processor.
-----------------------------------------------------------------
| TLBWR | Translation Lookaside Buffer Write Random |
|-----------|---------------------------------------------------|
| 010000 |CO| 0000 0000 0000 0000 000 | 000110 (6)|
------6------1-------------------19-----------------------6------
Format: TLBWR
Purpose: The G bit of the TLB is written with the logical AND of the G bits
in the EntryLo0 and EntryLo1 registers. The TLB entry pointed at by
the contents of the TLB Random register is loaded with the contents
of the EntryHi and EntryLo registers.
****************************************************************************
** Floating-point Unit, FPU (COP1) instructions **
****************************************************************************
fmt = 10000b (.S, Single) fmt = 10001b (.D, Double)
fmt = 10100b (.W, Word) fmt = 10101b (.L, Long)
-----------------------------------------------------------------
| ABS.fmt | floating-point ABSolute value |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000101 (5)|
------6----------5---------5---------5---------5----------6------
Format: ABS.S fd, fs
ABS.D fd, fs
Purpose: To compute the absolute value of an FP value.
-----------------------------------------------------------------
| ADD.fmt | floating-point ADD |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000000 (0)|
------6----------5---------5---------5---------5----------6------
Format: ADD.S fd, fs, ft
ADD.D fd, fs, ft
Purpose: To add FP values.
-----------------------------------------------------------------
| BC1F | Branch on FP False |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| 000|nd|tf| offset |
| | | | 0| 0| |
------6----------5-------3---1--1--------------16----------------
Format: BC1F offset
Purpose: To test an FP condition code and do a PC-relative
conditional branch.
-----------------------------------------------------------------
| BC1FL | Branch on FP False Likley |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| 000|nd|tf| offset |
| | | | 1| 0| |
------6----------5-------3---1--1--------------16----------------
Format: BC1FL offset
Purpose: To test an FP condition code and do a PC-relative conditional
branch; execute the delay slot only if the branch is taken.
-----------------------------------------------------------------
| BC1T | Branch on FP True |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| 000|nd|tf| offset |
| | | | 0| 1| |
------6----------5-------3---1--1--------------16----------------
Format: BC1T offset
Purpose: To test an FP condition code and do a PC-relative
conditional branch.
-----------------------------------------------------------------
| BC1TL | Branch on FP True Likley |
|-----------|---------------------------------------------------|
| 010001 |01000 (8)| 000|nd|tf| offset |
| | | | 1| 1| |
------6----------5-------3---1--1--------------16----------------
Format: BC1TL offset
Purpose: To test an FP condition code and do a PC-relative conditional
branch; execute the delay slot only if the branch is taken.
-----------------------------------------------------------------
| C.cond.fmt| floating-point Compare |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | 000 |00 |11 | cond |
------6----------5---------5---------5-------3----2---2-----4----
cond: 0000 = F (False)
0001 = UN (Unordered)
0010 = EQ (Equal)
0011 = UEQ (Unordered or Equal)
0100 = OLT (Ordered or Less Than)
0101 = ULT (Unordered or Less Than)
0110 = OLE (Ordered or Less than or Equal)
0111 = ULE (Unordered or Less than or Equal)
1000 = SF (Signaling False)
1001 = NGLE (Not Greater than or Less than or Equal)
1010 = SEQ (Signaling Equal)
1011 = NGL (Not Greater than or Less than)
1100 = LT (Less Than)
1101 = NGE (Not Greater than or Equal)
1110 = LE (Less than or Equal)
1111 = NGT (Not Greater Than)
Format: C.cond.S fs, ft
C.cond.D fs, ft
Purpose: To compare FP values and record the Boolean result in
a condition code.
-----------------------------------------------------------------
| CEIL.L.fmt| floating-point CEILing convert to Long fixed-point|
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001010 (10)|
------6----------5---------5---------5---------5----------6------
Format: CEIL.L.S fd, fs
CEIL.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding up.
-----------------------------------------------------------------
| CEIL.W.fmt| floating-point CEILing convert to Word fixed-point|
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001110 (14)|
------6----------5---------5---------5---------5----------6------
Format: CEIL.W.S fd, fs
CEIL.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding up.
-----------------------------------------------------------------
| CFC1 | Move control word From Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00010 (2)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: CFC1 rt, fs
Purpose: To copy a word from an FPU control register to a GPR.
Descrip: rt = fs
-----------------------------------------------------------------
| CTC1 | Move control word To Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00110 (6)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: CTC1 rt, fs
Purpose: To copy a word from a GPR to an FPU control register.
Descrip: fs = rt
-----------------------------------------------------------------
| CVT.D.fmt | floating-point ConVerT to Double floating-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100001 (33)|
------6----------5---------5---------5---------5----------6------
Format: CVT.D.S fd, fs
CVT.D.W fd, fs
CVT.D.L fd, fs
Purpose: To convert an FP or fixed-point value to double FP.
-----------------------------------------------------------------
| CVT.L.fmt | floating-point ConVerT to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100101 (37)|
------6----------5---------5---------5---------5----------6------
Format: CVT.L.S fd, fs
CVT.L.D fd, fs
Purpose: To convert an FP value to a 64-bit fixed-point.
-----------------------------------------------------------------
| CVT.S.fmt | floating-point ConVerT to Single floating-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100000 (32)|
------6----------5---------5---------5---------5----------6------
Format: CVT.S.D fd, fs
CVT.S.W fd, fs
CVT.S.L fd, fs
Purpose: To convert an FP or fixed-point value to single FP.
-----------------------------------------------------------------
| CVT.W.fmt | floating-point ConVerT to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |100100 (36)|
------6----------5---------5---------5---------5----------6------
Format: CVT.W.S fd, fs
CVT.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point.
-----------------------------------------------------------------
| DIV.fmt | floating-point DIVide |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000011 (3)|
------6----------5---------5---------5---------5----------6------
Format: DIV.S fd, fs, ft
DIV.D fd, fs, ft
Purpose: To divide FP values.
-----------------------------------------------------------------
| DMFC1 | Doubleword Move From Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00001 (1)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: DMFC1 rt, fs
Purpose: To copy a doubleword from an FPR to a GPR.
-----------------------------------------------------------------
| DMTC1 | Doubleword Move To Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00101 (5)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: DMTC1 rt, fs
Purpose: To copy a doubleword from a GPR to an FPR.
-----------------------------------------------------------------
|FLOOR.L.fmt| floating-point FLOOR convert to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001011 (11)|
------6----------5---------5---------5---------5----------6------
Format: FLOOR.L.S fd, fs
FLOOR.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding down.
-----------------------------------------------------------------
|FLOOR.W.fmt| floating-point FLOOR convert to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001111 (15)|
------6----------5---------5---------5---------5----------6------
Format: FLOOR.W.S fd, fs
FLOOR.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding down.
-----------------------------------------------------------------
| LDC1 | Load Doubleword to Floating-Point |
|-----------|---------------------------------------------------|
|110101 (53)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: LDC1 ft, offset(base)
Purpose: To load a doubleword from memory to an FPR.
Descrip: COP ft = doubleword[base+offset]
-----------------------------------------------------------------
| LWC1 | Load Word to Floating-Point |
|-----------|---------------------------------------------------|
|110001 (49)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: LWC1 ft, offset(base)
Purpose: To load a word from memory to an FPR.
Comment: LWC1 ft, offset(base) is equal to a L.S ft, offset(base)
Descrip: COP ft = word[base+offset]
-----------------------------------------------------------------
| MFC1 | Move Word From Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00000 (0)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MFC1 rt, fs
Purpose: To copy a word from an FPU (CP1) general register to a GPR.
Descrip: rt = COP fs
-----------------------------------------------------------------
| MOV.fmt | floating-point MOVe |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000110 (6)|
------6----------5---------5---------5---------5----------6------
Format: MOV.S fd, fs
MOV.D fd, fs
Purpose: To move an FP value between FPRs.
-----------------------------------------------------------------
| MTC1 | Move Word to Floating-Point |
|-----------|---------------------------------------------------|
| 010001 |00100 (4)| rt | fs | 0000 0000 000 |
------6----------5---------5---------5--------------11-----------
Format: MTC1 rt, fs
Purpose: To copy a word from a GPR to an FPU (CP1) general register.
Descrip: COP fs = rt
-----------------------------------------------------------------
| MUL.fmt | floating-point MULtiply |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000010 (2)|
------6----------5---------5---------5---------5----------6------
Format: MUL.S fd, fs, ft
MUL.D fd, fs, ft
Purpose: To multiply FP values.
-----------------------------------------------------------------
| NEG.fmt | floating-point NEGate |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000111 (7)|
------6----------5---------5---------5---------5----------6------
Format: NEG.S fd, fs
NEG.D fd, fs
Purpose: To negate an FP value.
-----------------------------------------------------------------
|ROUND.L.fmt| floating-point ROUND to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 001000 (8)|
------6----------5---------5---------5---------5----------6------
Format: ROUND.L.S fd, fs
ROUND.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding to nearest.
-----------------------------------------------------------------
|ROUND.W.fmt| floating-point ROUND to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001100 (12)|
------6----------5---------5---------5---------5----------6------
Format: ROUND.W.S fd, fs
ROUND.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding to nearest.
-----------------------------------------------------------------
| SDC1 | Store Doubleword from Floating-Point |
|-----------|---------------------------------------------------|
|111101 (61)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: SDC1 ft, offset(base)
Purpose: To store a doubleword from an FPR to memory.
Descrip: doubleword[base+offset] = COP rt
-----------------------------------------------------------------
| SQRT.fmt | floating-point SQuare RooT |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 000100 (4)|
------6----------5---------5---------5---------5----------6------
Format: SQRT.S fd, fs
SQRT.D fd, fs
Purpose: To compute the square root of an FP value.
-----------------------------------------------------------------
| SUB.fmt | floating-point SUBtract |
|-----------|---------------------------------------------------|
| 010001 | fmt | ft | fs | fd | 000001 (1)|
------6----------5---------5---------5---------5----------6------
Format: SUB.S fd, fs, ft
SUB.D fd, fs, ft
Purpose: To subtract FP values.
-----------------------------------------------------------------
| SWC1 | Store Word from Floating-Point |
|-----------|---------------------------------------------------|
|111001 (57)| base | ft | offset |
------6----------5---------5-------------------16----------------
Format: SWC1 ft, offset(base)
Purpose: To store a word from an FPR to memory.
Comment: SWC1 ft, offset(base) is equal to a S.S ft, offset(base)
Descrip: word[base+offset] = COP rt
-----------------------------------------------------------------
|TRUNC.L.fmt| floating-point TRUNCate to Long fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd | 001001 (9)|
------6----------5---------5---------5---------5----------6------
Format: TRUNC.L.S fd, fs
TRUNC.L.D fd, fs
Purpose: To convert an FP value to 64-bit fixed-point, rounding toward zero.
-----------------------------------------------------------------
|TRUNC.W.fmt| floating-point TRUNCate to Word fixed-point |
|-----------|---------------------------------------------------|
| 010001 | fmt | 00000 | fs | fd |001101 (13)|
------6----------5---------5---------5---------5----------6------
Format: TRUNC.W.S fd, fs
TRUNC.W.D fd, fs
Purpose: To convert an FP value to 32-bit fixed-point, rounding toward zero.
n64ops#c
Part C: R4300i opcode matrix
****************************************************************************
** Main CPU **
****************************************************************************
CPU: Instructions encoded by opcode field.
31---------26---------------------------------------------------0
| opcode | |
------6----------------------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ |
001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI |
010 | *3 | *4 | --- | --- | BEQL | BNEL | BLEZL | BGTZL |
011 | DADDI |DADDIU | LDL | LDR | --- | --- | --- | --- |
100 | LB | LH | LWL | LW | LBU | LHU | LWR | LWU |
101 | SB | SH | SWL | SW | SDL | SDR | SWR | CACHE |
110 | LL | LWC1 | --- | --- | LLD | LDC1 | LDC2 | LD |
111 | SC | SWC1 | --- | --- | SCD | SDC1 | SDC2 | SD |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = SPECIAL, see SPECIAL list *2 = REGIMM, see REGIMM list
*3 = COP0 *4 = COP1
SPECIAL: Instr. encoded by function field when opcode field = SPECIAL.
31---------26------------------------------------------5--------0
| = SPECIAL | | function|
------6----------------------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | SLL | --- | SRL | SRA | SLLV | --- | SRLV | SRAV |
001 | JR | JALR | --- | --- |SYSCALL| BREAK | --- | SYNC |
010 | MFHI | MTHI | MFLO | MTLO | DSLLV | --- | DSRLV | DSRAV |
011 | MULT | MULTU | DIV | DIVU | DMULT | DMULTU| DDIV | DDIVU |
100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR |
101 | --- | --- | SLT | SLTU | DADD | DADDU | DSUB | DSUBU |
110 | TGE | TGEU | TLT | TLTU | TEQ | --- | TNE | --- |
111 | DSLL | --- | DSRL | DSRA |DSLL32 | --- |DSRL32 |DSRA32 |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
REGIMM: Instructions encoded by the rt field when opcode field = REGIMM.
31---------26----------20-------16------------------------------0
| = REGIMM | | rt | |
------6---------------------5------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | BLTZ | BGEZ | BLTZL | BGEZL | --- | --- | --- | --- |
01 | TGEI | TGEIU | TLTI | TLTIU | TEQI | --- | TNEI | --- |
10 | BLTZAL| BGEZAL|BLTZALL|BGEZALL| --- | --- | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
****************************************************************************
** COP0 **
****************************************************************************
COP0: Instructions encoded by the fmt field when opcode = COP0.
31--------26-25------21 ----------------------------------------0
| = COP0 | fmt | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | MFC0 | --- | --- | --- | MTC0 | --- | --- | --- |
01 | --- | --- | --- | --- | --- | --- | --- | --- |
10 | *1 | --- | --- | --- | --- | --- | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = TLB instr, see TLB list
TLB: Instructions encoded by the function field when opcode
= COP0 and fmt = TLB.
31--------26-25------21 -------------------------------5--------0
| = COP0 | = TLB | | function|
------6----------5-----------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | --- | TLBR | TLBWI | --- | --- | --- | TLBWR | --- |
001 | TLBP | --- | --- | --- | --- | --- | --- | --- |
010 | --- | --- | --- | --- | --- | --- | --- | --- |
011 | ERET | --- | --- | --- | --- | --- | --- | --- |
100 | --- | --- | --- | --- | --- | --- | --- | --- |
101 | --- | --- | --- | --- | --- | --- | --- | --- |
110 | --- | --- | --- | --- | --- | --- | --- | --- |
111 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
****************************************************************************
** COP1 - Floating Point Unit (FPU) **
****************************************************************************
COP1: Instructions encoded by the fmt field when opcode = COP1.
31--------26-25------21 ----------------------------------------0
| = COP1 | fmt | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | MFC1 | DMFC1 | CFC1 | --- | MTC1 | DMTC1 | CTC1 | --- |
01 | *1 | --- | --- | --- | --- | --- | --- | --- |
10 | *2 | *3 | --- | --- | *4 | *5 | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = BC instructions, see BC1 list
*2 = S instr, see FPU list *3 = D instr, see FPU list
*4 = W instr, see FPU list *5 = L instr, see FPU list
BC1: Instructions encoded by the nd and tf fields when opcode
= COP1 and fmt = BC
31--------26-25------21 ---17--16-------------------------------0
| = COP1 | = BC | |nd|tf| |
------6----------5-----------1--1--------------------------------
|---0---|---1---| tf
0 | BC1F | BC1T |
1 | BC1FL | BC1TL |
nd |-------|-------|
FPU: Instructions encoded by the function field when opcode = COP1
and fmt = S
31--------26-25------21 -------------------------------5--------0
| = COP1 | = S | | function|
------6----------5-----------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | ADD | SUB | MUL | DIV | SQRT | ABS | MOV | NEG |
001 |ROUND.L|TRUNC.L| CEIL.L|FLOOR.L|ROUND.W|TRUNC.W| CEIL.W|FLOOR.W|
010 | --- | --- | --- | --- | --- | --- | --- | --- |
011 | --- | --- | --- | --- | --- | --- | --- | --- |
100 | --- | CVT.D | --- | --- | CVT.W | CVT.L | --- | --- |
101 | --- | --- | --- | --- | --- | --- | --- | --- |
110 | C.F | C.UN | C.EQ | C.UEQ | C.OLT | C.ULT | C.OLE | C.ULE |
111 | C.SF | C.NGLE| C.SEQ | C.NGL | C.LT | C.NGE | C.LE | C.NGT |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
FPU: Instructions encoded by the function field when opcode = COP1
and fmt = D
31--------26-25------21 -------------------------------5--------0
| = COP1 | = D | | function|
------6----------5-----------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | ADD | SUB | MUL | DIV | SQRT | ABS | MOV | NEG |
001 |ROUND.L|TRUNC.L| CEIL.L|FLOOR.L|ROUND.W|TRUNC.W| CEIL.W|FLOOR.W|
010 | --- | --- | --- | --- | --- | --- | --- | --- |
011 | --- | --- | --- | --- | --- | --- | --- | --- |
100 | CVT.S | --- | --- | --- | CVT.W | CVT.L | --- | --- |
101 | --- | --- | --- | --- | --- | --- | --- | --- |
110 | C.F | C.UN | C.EQ | C.UEQ | C.OLT | C.ULT | C.OLE | C.ULE |
111 | C.SF | C.NGLE| C.SEQ | C.NGL | C.LT | C.NGE | C.LE | C.NGT |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
FPU: Instructions encoded by the function field when opcode = COP1
and fmt = W
31--------26-25------21 -------------------------------5--------0
| = COP1 | = W | | function|
------6----------5-----------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | --- | --- | --- | --- | --- | --- | --- | --- |
001 | --- | --- | --- | --- | --- | --- | --- | --- |
010 | --- | --- | --- | --- | --- | --- | --- | --- |
011 | --- | --- | --- | --- | --- | --- | --- | --- |
100 | CVT.S | CVT.D | --- | --- | --- | --- | --- | --- |
101 | --- | --- | --- | --- | --- | --- | --- | --- |
110 | --- | --- | --- | --- | --- | --- | --- | --- |
111 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
FPU: Instructions encoded by the function field when opcode = COP1
and fmt = L
31--------26-25------21 -------------------------------5--------0
| = COP1 | = L | | function|
------6----------5-----------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | --- | --- | --- | --- | --- | --- | --- | --- |
001 | --- | --- | --- | --- | --- | --- | --- | --- |
010 | --- | --- | --- | --- | --- | --- | --- | --- |
011 | --- | --- | --- | --- | --- | --- | --- | --- |
100 | CVT.S | CVT.D | --- | --- | --- | --- | --- | --- |
101 | --- | --- | --- | --- | --- | --- | --- | --- |
110 | --- | --- | --- | --- | --- | --- | --- | --- |
111 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
n64ops#d
Part D: Brief list of RSP opcodes
All information on the RSP was provided by my friend Zilmar.
Names of the opcodes are just guessings, also maybe not all of these opcodes
really exist on the Nintendo 64, since information on the opcodes are from
the SGI hardware. Bear with us, updates will cover the RSP more correctly.
****************************************************************************
** Explanations **
****************************************************************************
v<dest> = The destination vector register, where the result will be placed.
del = Specifies the destination element to be used.
offset = 16-bit additional offset to use from a base register.
base = The base GPR to use for load/store operations.
v<s1> = Source vector register.
v<s2> = Source vector register.
el = Specifies the element to be used on a source vector register.
****************************************************************************
** Load and Store Instructions **
****************************************************************************
LBV $v<dest>[del], offset(base) Load byte to vector
LSV $v<dest>[del], offset(base) Load short (halfword) to vector
LLV $v<dest>[del], offset(base) Load long (word) to vector
LDV $v<dest>[del], offset(base) Load double (doubleword) to vector
LQV $v<dest>[del], offset(base) Load quad (quadword) to vector
LRV $v<dest>[del], offset(base) Load rest to vector
LPV $v<dest>[del], offset(base) Load packed to vector
LUV $v<dest>[del], offset(base) Load unpacked to vector
LHV $v<dest>[del], offset(base) Load half to vector
LFV $v<dest>[del], offset(base) Load fourth to vector
LWV $v<dest>[del], offset(base) Load wrap to vector
LTV $v<dest>[del], offset(base) Load transpose to vector
SBV $v<dest>[del], offset(base) Store byte from vector
SSV $v<dest>[del], offset(base) Store short (halfword) from vector
SLV $v<dest>[del], offset(base) Store long (word) from vector
SDV $v<dest>[del], offset(base) Store double (doubleword) from vector
SQV $v<dest>[del], offset(base) Store quad (quadword) from vector
SRV $v<dest>[del], offset(base) Store rest from vector
SPV $v<dest>[del], offset(base) Store packed from vector
SUV $v<dest>[del], offset(base) Store unpacked from vector
SHV $v<dest>[del], offset(base) Store half from vector
SFV $v<dest>[del], offset(base) Store fourth from vector
SWV $v<dest>[del], offset(base) Store wrap from vector
STV $v<dest>[del], offset(base) Store transpose from vector
****************************************************************************
** Vector Instructions **
****************************************************************************
VMULF $v<dest>, $v<s1>, $v<s2>[el] Vector (Frac) Multiply
VMULU $v<dest>, $v<s1>, $v<s2>[el] Vector (Unsigned Frac) Multiply
VRNDP $v<dest>, $v<s1>, $v<s2>[el] Vector DCT Round (+)
VMULQ $v<dest>, $v<s1>, $v<s2>[el] Vector (Integer) Multiply
VMUDL $v<dest>, $v<s1>, $v<s2>[el] Vector low multiply
VMUDM $v<dest>, $v<s1>, $v<s2>[el] Vector mid-m multiply
VMUDN $v<dest>, $v<s1>, $v<s2>[el] Vector mid-n multiply
VMUDH $v<dest>, $v<s1>, $v<s2>[el] Vector high multiply
VMACF $v<dest>, $v<s1>, $v<s2>[el] Vector (Frac) Multiply Accumulate
VMACU $v<dest>, $v<s1>, $v<s2>[el] Vector (Unsigned Frac) Multiply Accumulate
VRNDN $v<dest>, $v<s1>, $v<s2>[el] Vector DCT Round (-)
VMACQ $v<dest>, $v<s1>, $v<s2>[el] Vector (Integer) Multiply Accumulate
VMADL $v<dest>, $v<s1>, $v<s2>[el] Vector low multiply accumulate
VMADM $v<dest>, $v<s1>, $v<s2>[el] Vector mid-m multiply accumulate
VMADN $v<dest>, $v<s1>, $v<s2>[el] Vector mid-n multiply accumulate
VMADH $v<dest>, $v<s1>, $v<s2>[el] Vector high multiply accumulate
I don't have instruction encoding on the following:
VADD $v<dest>, $v<s1>, $v<s2>[el] Vector Add
VSUB $v<dest>, $v<s1>, $v<s2>[el] Vector Subtract
VABS $v<dest>, $v<s1>, $v<s2>[el] Vector Absolute Value
VADDC $v<dest>, $v<s1>, $v<s2>[el] Vector ADDC
VSUBC $v<dest>, $v<s1>, $v<s2>[el] Vector SUBC
VLT ? Vector Less Than
VEQ ? Vector Equal To
VNE ? Vector Not Equal To
VGE ? Vector Greater Than or Equal To
VCL ? Vector Clip Low
VCH ? Vector Clip High
VCR ? Vector, 1's Complement Clip
VMRG ? Vector Merge
VAND ? Vector Logical AND
VNAND ? Vector Logical NOT AND
VOR ? Vector Logical OR
VNOR ? Vector Logical NOT OR
VXOR ? Vector Logical Exclusive OR
VNXOR ? Vector Logical NOT Exclusive OR
VRCP ? Single Precision, Lookup Source, Write Result
VRCPL ? Lookup Source and Previous, Write Result
VRCPH ? Set Source, Write Previous Result
VMOV ? Vector Move
VRSQ ? Single Precision, Lookup Source, Write Result
VRSQL ? Lookup Source and Previous, Write Result
VRSQH ? Set Source, Write Previous Result
n64ops#e
Part E: Detailed list of RSP opcodes
All information on the RSP was provided by my friend Zilmar.
****************************************************************************
** Registers **
****************************************************************************
Main GPR registers:
-------------------
00h = r0/reg0 08h = t0/reg8 10h = s0/reg16 18h = t8/reg24
01h = at/reg1 09h = t1/reg9 11h = s1/reg17 19h = t9/reg25
02h = v0/reg2 0Ah = t2/reg10 12h = s2/reg18 1Ah = k0/reg26
03h = v1/reg3 0Bh = t3/reg11 13h = s3/reg19 1Bh = k1/reg27
04h = a0/reg4 0Ch = t4/reg12 14h = s4/reg20 1Ch = gp/reg28
05h = a1/reg5 0Dh = t5/reg13 15h = s5/reg21 1Dh = sp/reg29
06h = a2/reg6 0Eh = t6/reg14 16h = s6/reg22 1Eh = s8/reg30
07h = a3/reg7 0Fh = t7/reg15 17h = s7/reg23 1Fh = ra/reg31
Vector registers:
-----------------
00h = $v0 08h = $v8 10h = $v16 18h = $v24
01h = $v1 09h = $v9 11h = $v17 19h = $v25
02h = $v2 0Ah = $v10 12h = $v18 1Ah = $v26
03h = $v3 0Bh = $v11 13h = $v19 1Bh = $v27
04h = $v4 0Ch = $v12 14h = $v20 1Ch = $v28
05h = $v5 0Dh = $v13 15h = $v21 1Dh = $v29
06h = $v6 0Eh = $v14 16h = $v22 1Eh = $v30
07h = $v7 0Fh = $v15 17h = $v23 1Fh = $v31
****************************************************************************
** Load and Store Instructions **
****************************************************************************
+-----------+---------------------------------------------------+
| LBV | Load byte to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00000 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LBV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LSV | Load short (halfword) to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00001 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LSV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LLV | Load long (word) to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00010 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LLV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LDV | Load double to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00011 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LDV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LQV | Load quadword to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00100 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LQV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LRV | Load rest to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00101 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LRV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LPV | Load packed to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00110 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LPV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LUV | Load unpacked to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00111 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LUV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LHV | Load half to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01000 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LHV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LFV | Load fourth to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01001 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LFV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LWV | Load wrap to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01010 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LWV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| LTV | Load transpose to vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01011 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: LTV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SBV | Store byte from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00000 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SBV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SSV | Store short (halfword) from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00001 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SSV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SLV | Store long (word) from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00010 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SLV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SDV | Store double (doubleword) from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00011 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SDV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SQV | Store quad (quadword) from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00100 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SQV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SRV | Store rest from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00101 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SRV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SPV | Store packed from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00110 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SPV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SUV | Store unpacked from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 00111 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SUV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SHV | Store half from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01000 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SHV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SFV | Store fourth from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01001 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SFV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| SWV | Store wrap from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01010 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: SWV $v<dest>[del], offset(base)
+-----------+---------------------------------------------------+
| STV | Store transpose from vector |
+-----------+---------+---------+---------+-------+-+-----------+
| 110010 | base | dest | 01011 | del |0| offset |
+-----6-----+----5----+----5----+----5----+---4---+1+-----6-----+
Format: STV $v<dest>[del], offset(base)
****************************************************************************
** Vector instructions **
****************************************************************************
-----------------------------------------------------------------
| VMULF | Vector (Frac) Multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000000 |
------6------1----4--------5---------5---------5----------6------
Format: VMULF $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMULU | Vector (Unsigned Frac) Multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000001 |
------6------1----4--------5---------5---------5----------6------
Format: VMULU $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VRNDP | Vector DCT Round (+) |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000010 |
------6------1----4--------5---------5---------5----------6------
Format: VRNDP $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMULQ | Vector (Integer) Multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000011 |
------6------1----4--------5---------5---------5----------6------
Format: VMULQ $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMUDL | Vector low multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000100 |
------6------1----4--------5---------5---------5----------6------
Format: VMUDL $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMUDM | Vector mid-m multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000101 |
------6------1----4--------5---------5---------5----------6------
Format: VMUDM $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMUDN | Vector mid-n multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000110 |
------6------1----4--------5---------5---------5----------6------
Format: VMUDN $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMUDH | Vector high multiply |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 000111 |
------6------1----4--------5---------5---------5----------6------
Format: VMUDH $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMACF | Vector (Frac) Multiply Accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001000 |
------6------1----4--------5---------5---------5----------6------
Format: VMACF $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMACU | Vector (Unsigned Frac) Multiply Accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001001 |
------6------1----4--------5---------5---------5----------6------
Format: VMACU $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VRNDN | Vector DCT Round (-) |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001010 |
------6------1----4--------5---------5---------5----------6------
Format: VRNDN $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMACQ | Vector (Integer) Multiply Accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001011 |
------6------1----4--------5---------5---------5----------6------
Format: VMACQ $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMADL | Vector low multiply accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001100 |
------6------1----4--------5---------5---------5----------6------
Format: VMADL $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMADM | Vector mid-m multiply accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001101 |
------6------1----4--------5---------5---------5----------6------
Format: VMADM $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMADN | Vector mid-n multiply accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001110 |
------6------1----4--------5---------5---------5----------6------
Format: VMADN $v<dest>, $v<s1>, $v<s2>[el]
-----------------------------------------------------------------
| VMADH | Vector high multiply accumulate |
|-----------|---------------------------------------------------|
| 010010 |1| el | s2 | s1 | dest | 001111 |
------6------1----4--------5---------5---------5----------6------
Format: VMADH $v<dest>, $v<s1>, $v<s2>[el]
n64ops#f
Part F: RSP opcode matrix
All information on the RSP was provided by my friend Zilmar.
****************************************************************************
** Main CPU **
****************************************************************************
CPU: Instructions encoded by opcode field.
31---------26---------------------------------------------------0
| opcode | |
------6----------------------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | *1 | *2 | J | JAL | BEQ | BNE | BLEZ | BGTZ |
001 | ADDI | ADDIU | SLTI | SLTIU | ANDI | ORI | XORI | LUI |
010 | *3 | --- | *4 | --- | --- | --- | --- | --- |
011 | --- | --- | --- | --- | --- | --- | --- | --- |
100 | LB | LH | --- | LW | LBU | LHU | --- | --- |
101 | SB | SH | --- | SW | --- | --- | --- | --- |
110 | --- | --- | *LWC2 | --- | --- | --- | --- | --- |
111 | --- | --- | *SWC2 | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = SPECIAL, see SPECIAL list *2 = REGIMM, see REGIMM list
*3 = COP0 *4 = COP2
*LWC2 = RSP Load instructions *SWC2 = RSP Store instructions
SPECIAL: Instr. encoded by function field when opcode field = SPECIAL.
31---------26-----------------------------------------5---------0
| = SPECIAL | | function|
------6----------------------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | SLL | --- | SRL | SRA | SLLV | --- | SRLV | SRAV |
001 | JR | JALR | --- | --- | --- | BREAK | --- | --- |
010 | --- | --- | --- | --- | --- | --- | --- | --- |
011 | --- | --- | --- | --- | --- | --- | --- | --- |
100 | ADD | ADDU | SUB | SUBU | AND | OR | XOR | NOR |
101 | --- | --- | SLT | SLTU | --- | --- | --- | --- |
110 | --- | --- | --- | --- | --- | --- | --- | --- |
111 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
REGIMM: Instructions encoded by the rt field when opcode field = REGIMM.
31---------26----------20-------16------------------------------0
| = REGIMM | | rt | |
------6---------------------5------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | BLTZ | BGEZ | --- | --- | --- | --- | --- | --- |
01 | --- | --- | --- | --- | --- | --- | --- | --- |
10 |BLTZAL |BGEZAL | --- | --- | --- | --- | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
****************************************************************************
** COP0 **
****************************************************************************
COP0: Instructions encoded by the fmt field when opcode = COP0.
31--------26-25------21 ----------------------------------------0
| 010000 | fmt | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | MFC0 | --- | --- | --- | MTC0 | --- | --- | --- |
01 | --- | --- | --- | --- | --- | --- | --- | --- |
10 | --- | --- | --- | --- | --- | --- | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
****************************************************************************
** COP2 - Reality Coprocessor (RCP) **
****************************************************************************
COP2: Instructions encoded by the fmt field when opcode = COP2.
31--------26-25------21 ----------------------------------------0
| = COP2 | fmt | |
------6----------5-----------------------------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | MFC2 | --- | CFC2 | --- | MTC2 | --- | CTC2 | --- |
01 | --- | --- | --- | --- | --- | --- | --- | --- |
10 | *1 | *1 | *1 | *1 | *1 | *1 | *1 | *1 |
11 | *1 | *1 | *1 | *1 | *1 | *1 | *1 | *1 |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
*1 = Vector opcode
RSP Load: Instr. encoded by rd field when opcode field = LWC2
31---------26-------------------15-------11---------------------0
| 110010 | | rd | |
------6-----------------------------5----------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | LBV | LSV | LLV | LDV | LQV | LRV | LPV | LUV |
01 | LHV | LFV | LWV | LTV | --- | --- | --- | --- |
10 | --- | --- | --- | --- | --- | --- | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
RSP Store: Instr. encoded by rd field when opcode field = SWC2
31---------26-------------------15-------11---------------------0
| 111010 | | rd | |
------6-----------------------------5----------------------------
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
00 | SBV | SSV | SLV | SDV | SQV | SRV | SPV | SUV |
01 | SHV | SFV | SWV | STV | --- | --- | --- | --- |
10 | --- | --- | --- | --- | --- | --- | --- | --- |
11 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
Vector opcodes: Instr. encoded by the function field when opcode = COP2.
31---------26---25------------------------------------5---------0
| = COP2 | 1 | | function|
------6-------1--------------------------------------------6-----
|--000--|--001--|--010--|--011--|--100--|--101--|--110--|--111--| lo
000 | VMULF | VMULU | VRNDP | VMULQ | VMUDL | VMUDM | VMUDN | VMUDH |
001 | VMACF | VMACU | VRNDN | VMACQ | VMADL | VMADM | VMADN | VMADH |
010 | VADD | VSUB | VSUT? | VABS | VADDC | VSUBC | VADDB?| VSUBB?|
011 | VACCB?| VSUCB?| VSAD? | VSAC? | VSUM? | VSAW | --- | --- |
100 | VLT | VEQ | VNE | VGE | VCL | VCH | VCR | VMRG |
101 | VAND | VNAND | VOR | VNOR | VXOR | VNXOR | --- | --- |
110 | VRCP | VRCPL | VRCPH | VMOV | VRSQ | VRSQL | VRSQH | --- |
110 | --- | --- | --- | --- | --- | --- | --- | --- |
hi |-------|-------|-------|-------|-------|-------|-------|-------|
Comment: Those with a ? in the end of them may not exist
n64ops#g
Part G: ROM header information
* Mr Backup Z64 (.BIN or .Z64 files) uses a Low/High byte format
(Big endian), wich is the "correct" format to read from.
* Doctor V64 (.V64, .N64 or .U64 files) uses a High/Low byte format
(Middle endian), so each word are byte flipped, like this:
"ETTSNI G"
When it should look like this:
"TESTING "
To solve this, rotate each word by 8 bits.
----------------------------------------------------------------------------
The addresses below is only valid for ROM's in Low/High
format, eg: Mr Backup Z64 ROM's. You have to byteswap Doctor
V64 ROM's before you can read data that makes any sense.
----------------------------------------------------------------------------
0000h (1 byte): initial PI_BSB_DOM1_LAT_REG value (0x80)
0001h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x37)
0002h (1 byte): initial PI_BSB_DOM1_PWD_REG value (0x12)
0003h (1 byte): initial PI_BSB_DOM1_PGS_REG value (0x40)
0004h - 0007h (1 dword): ClockRate
0008h - 000Bh (1 dword): Program Counter (PC)
000Ch - 000Fh (1 dword): Release
0010h - 0013h (1 dword): CRC1
0014h - 0017h (1 dword): CRC2
0018h - 001Fh (2 dwords): Unknown (0x0000000000000000)
0020h - 0033h (20 bytes): Image name
Padded with 0x00 or spaces (0x20)
0034h - 0037h (1 dword): Unknown (0x00000000)
0038h - 003Bh (1 dword): Manufacturer ID
0x0000004E = Nintendo ('N')
003Ch - 003Dh (1 word): Cartridge ID
003Eh - 003Fh (1 word): Country code
0x4400 = Germany ('D')
0x4500 = USA ('E')
0x4A00 = Japan ('J')
0x5000 = Europe ('P')
0x5500 = Australia ('U')
0040h - 0FFFh (1008 dwords): Boot code
n64ops#h
Part H: Nintendo 64 memory map
*************************************************************************
** Overview **
*************************************************************************
0x0000 0000 to 0x03EF FFFF RDRAM Memory
0x03F0 0000 to 0x03FF FFFF RDRAM Registers
0x0400 0000 to 0x040F FFFF SP Registers
0x0410 0000 to 0x041F FFFF DP Command Registers
0x0420 0000 to 0x042F FFFF DP Span Registers
0x0430 0000 to 0x043F FFFF MIPS Interface (MI) Registers
0x0440 0000 to 0x044F FFFF Video Interface (VI) Registers
0x0450 0000 to 0x045F FFFF Audio Interface (AI) Registers
0x0460 0000 to 0x046F FFFF Peripheral Interface (PI) Registers
0x0470 0000 to 0x047F FFFF RDRAM Interface (RI) Registers
0x0480 0000 to 0x048F FFFF Serial Interface (SI) Registers
0x0490 0000 to 0x04FF FFFF Unused
0x0500 0000 to 0x05FF FFFF Cartridge Domain 2 Address 1
0x0600 0000 to 0x07FF FFFF Cartridge Domain 1 Address 1
0x0800 0000 to 0x0FFF FFFF Cartridge Domain 2 Address 2
0x1000 0000 to 0x1FBF FFFF Cartridge Domain 1 Address 2
0x1FC0 0000 to 0x1FC0 07BF PIF Boot ROM
0x1FC0 07C0 to 0x1FC0 07FF PIF RAM
0x1FC0 0800 to 0x1FCF FFFF Reserved
0x1FD0 0000 to 0x7FFF FFFF Cartridge Domain 1 Address 3
0x8000 0000 to 0xFFFF FFFF External SysAD Device
*************************************************************************
** Detailed **
*************************************************************************
0x0000 0000 to 0x03EF FFFF RDRAM memory:
-----------------------------------------
0x0000 0000 to 0x001F FFFF RDRAM range 0
0x0020 0000 to 0x003F FFFF RDRAM range 1
0x0040 0000 to 0x03EF FFFF Unused
0x03F0 0000 to 0x03FF FFFF RDRAM registers:
--------------------------------------------
RDRAM_BASE_REG - 0x03F00000
0x03F0 0000 to 0x03F0 0003 RDRAM_CONFIG_REG or
RDRAM_DEVICE_TYPE_REG
0x03F0 0004 to 0x03F0 0007 RDRAM_DEVICE_ID_REG
0x03F0 0008 to 0x03F0 000B RDRAM_DELAY_REG
0x03F0 000C to 0x03F0 000F RDRAM_MODE_REG
0x03F0 0010 to 0x03F0 0013 RDRAM_REF_INTERVAL_REG
0x03F0 0014 to 0x03F0 0017 RDRAM_REF_ROW_REG
0x03F0 0018 to 0x03F0 001B RDRAM_RAS_INTERVAL_REG
0x03F0 001C to 0x03F0 001F RDRAM_MIN_INTERVAL_REG
0x03F0 0020 to 0x03F0 0023 RDRAM_ADDR_SELECT_REG
0x03F0 0024 to 0x03F0 0027 RDRAM_DEVICE_MANUF_REG
0x03F0 0028 to 0x03FF FFFF Unknown
0x0400 0000 to 0x0400 FFFF SP registers:
-----------------------------------------
SP_BASE_REG - 0x04040000
0x0400 0000 to 0x0400 0FFF SP_DMEM read/write
0x0400 1000 to 0x0400 1FFF SP_IMEM read/write
0x0400 2000 to 0x0403 FFFF Unused
0x0404 0000 to 0x0404 0003 SP_MEM_ADDR_REG
Master, SP memory address
(RW): [11:0] DMEM/IMEM address
[12] 0=DMEM,1=IMEM
0x0404 0004 to 0x0404 0007 SP_DRAM_ADDR_REG
Slave, SP DRAM DMA address
(RW): [23:0] RDRAM address
0x0404 0008 to 0x0404 000B SP_RD_LEN_REG
SP read DMA length
(RW): [11:0] length
[19:12] count
[31:20] skip
direction: I/DMEM <- RDRAM
0x0404 000C to 0x0404 000F SP_WR_LEN_REG
SP write DMA length
(RW): [11:0] length
[19:12] count
[31:20] skip
direction: I/DMEM to RDRAM
0x0404 0010 to 0x0404 0013 SP_STATUS_REG
SP status
(W): [0] clear halt (R): [0] halt
[1] set halt [1] broke
[2] clear broke [2] dma busy
[3] clear intr [3] dma full
[4] set intr [4] io full
[5] clear sstep [5] single step
[6] set sstep [6] interrupt on break
[7] clear intr on break [7] signal 0 set
[8] set intr on break [8] signal 1 set
[9] clear signal 0 [9] signal 2 set
[10] set signal 0 [10] signal 3 set
[11] clear signal 1 [11] signal 4 set
[12] set signal 1 [12] signal 5 set
[13] clear signal 2 [13] signal 6 set
[14] set signal 2 [14] signal 7 set
[15] clear signal 3
[16] set signal 3
[17] clear signal 4
[18] set signal 4
[19] clear signal 5
[20] set signal 5
[21] clear signal 6
[22] set signal 6
[23] clear signal 7
[24] set signal 7
0x0404 0014 to 0x0404 0017 SP_DMA_FULL_REG
SP DMA full
(R): [0] valid bit
dma full
0x0404 0018 to 0x0404 001B SP_DMA_BUSY_REG
SP DMA busy
(R): [0] valid bit
dma busy
0x0404 001C to 0x0404 001F SP_SEMAPHORE_REG
SP semaphore
(R): [0] semaphore flag (set on read)
(W): [] clear semaphore flag
0x0404 0020 to 0x0407 FFFF Unused
0x0408 0000 to 0x0408 0003 SP_PC_REG
SP PC
(RW): [11:0] program counter
0x0408 0004 to 0x0408 0007 SP_IBIST_REG
SP IMEM BIST REG
(W): [0] BIST check (R): [0] BIST check
[1] BIST go [1] BIST go
[2] BIST clear [2] BIST done
[6:3] BIST fail
0x0408 0008 to 0x040F FFFF Unused
0x0410 0000 to 0x041F FFFF DP command registers:
-------------------------------------------------
DPC_BASE_REG - 0x04100000
0x0410 0000 to 0x0410 0003 DPC_START_REG
DP CMD DMA start
(RW): [23:0] DMEM/RDRAM start address
0x0410 0004 to 0x0410 0007 DPC_END_REG
DP CMD DMA end
(RW): [23:0] DMEM/RDRAM end address
0x0410 0008 to 0x0410 000B DPC_CURRENT_REG
DP CMD DMA end
(R): [23:0] DMEM/RDRAM current address
0x0410 000C to 0x0410 000F DPC_STATUS_REG
DP CMD status
(W): [0] clear xbus_dmem_dma (R): [0] xbus_dmem_dma
[1] set xbus_dmem_dma [1] freeze
[2] clear freeze [2] flush
[3] set freeze [3] start gclk
[4] clear flush [4] tmem busy
[5] set flush [5] pipe busy
[6] clear tmem ctr [6] cmd busy
[7] clear pipe ctr [7] cbuf ready
[8] clear cmd ctr [8] dma busy
[9] clear clock ctr [9] end valid
[10] start valid
0x0410 0010 to 0x0410 0013 DPC_CLOCK_REG
DP clock counter
(R): [23:0] clock counter
0x0410 0014 to 0x0410 0017 DPC_BUFBUSY_REG
DP buffer busy counter
(R): [23:0] clock counter
0x0410 0018 to 0x0410 001B DPC_PIPEBUSY_REG
DP pipe busy counter
(R): [23:0] clock counter
0x0410 001C to 0x0410 001F DPC_TMEM_REG
DP TMEM load counter
(R): [23:0] clock counter
0x0410 0020 to 0x041F FFFF Unused
0x0420 0000 to 0x042F FFFF DP span registers:
----------------------------------------------
DPS_BASE_REG - 0x04200000
0x0420 0000 to 0x0420 0003 DPS_TBIST_REG
DP tmem bist
(W): [0] BIST check (R): [0] BIST check
[1] BIST go [1] BIST go
[2] BIST clear [2] BIST done
[10:3] BIST fail
0x0420 0004 to 0x0420 0007 DPS_TEST_MODE_REG
DP span test mode
(RW): [0] Span buffer test access enable
0x0420 0008 to 0x0420 000B DPS_BUFTEST_ADDR_REG
DP span buffer test address
(RW): [6:0] bits
0x0420 000C to 0x0420 000F DPS_BUFTEST_DATA_REG
DP span buffer test data
(RW): [31:0] span buffer data
0x0420 0010 to 0x042F FFFF Unused
0x0430 0000 to 0x043F FFFF MIPS interface (MI) registers:
----------------------------------------------------------
MI_BASE_REG - 0x04300000
0x0430 0000 to 0x0430 0003 MI_INIT_MODE_REG or MI_MODE_REG
MI init mode
(W): [6:0] init length (R): [6:0] init length
[7] clear init mode [7] init mode
[8] set init mode [8] ebus test mode
[9/10] clr/set ebus test mode [9] RDRAM reg mode
[11] clear DP interrupt
[12] clear RDRAM reg
[13] set RDRAM reg mode
0x0430 0004 to 0x0430 0007 MI_VERSION_REG or MI_NOOP_REG
MI version
(R): [7:0] io
[15:8] rac
[23:16] rdp
[31:24] rsp
0x0430 0008 to 0x0430 000B MI_INTR_REG
MI interrupt
(R): [0] SP intr
[1] SI intr
[2] AI intr
[3] VI intr
[4] PI intr
[5] DP intr
0x0430 000C to 0x0430 000F MI_INTR_MASK_REG
MI interrupt mask
(W): [0/1] clear/set SP mask (R): [0] SP intr mask
[2/3] clear/set SI mask [1] SI intr mask
[4/5] clear/set AI mask [2] AI intr mask
[6/7] clear/set VI mask [3] VI intr mask
[8/9] clear/set PI mask [4] PI intr mask
[10/11] clear/set DP mask [5] DP intr mask
0x0430 0010 to 0x043F FFFF Unused
0x0440 0000 to 0x044F FFFF Video interface (VI) registers:
-----------------------------------------------------------
VI_BASE_REG - 0x04400000
0x0440 0000 to 0x0440 0003 VI_STATUS_REG or VI_CONTROL_REG
VI status/control
(RW): [1:0] type[1:0] (pixel size)
0: blank (no data, no sync)
1: reserved
2: 5/5/5/3 ("16" bit)
3: 8/8/8/8 (32 bit)
[2] gamma_dither_enable (normally on, unless "special effect")
[3] gamma_enable (normally on, unless MPEG/JPEG)
[4] divot_enable (normally on if antialiased,
unless decal lines)
[5] reserved - always off
[6] serrate (always on if interlaced, off if not)
[7] reserved - diagnostics only
[9:8] anti-alias (aa) mode[1:0]
0: aa & resamp (always fetch extra lines)
1: aa & resamp (fetch extra lines if needed)
2: resamp only (treat as all fully covered)
3: neither (replicate pixels, no interpolate)
[11] reserved - diagnostics only
[15:12] reserved
0x0440 0004 to 0x0440 0007 VI_ORIGIN_REG or VI_DRAM_ADDR_REG
VI origin
(RW): [23:0] frame buffer origin in bytes
0x0440 0008 to 0x0440 000B VI_WIDTH_REG or VI_H_WIDTH_REG
VI width
(RW): [11:0] frame buffer line width in pixels
0x0440 000C to 0x0440 000F VI_INTR_REG or VI_V_INTR_REG
VI vertical intr
(RW): [9:0] interrupt when current half-line = V_INTR
0x0440 0010 to 0x0440 0013 VI_CURRENT_REG or VI_V_CURRENT_LINE_REG
VI current vertical line
(RW): [9:0] current half line, sampled once per line (the lsb of
V_CURRENT is constant within a field, and in
interlaced modes gives the field number - which is
constant for non-interlaced modes)
- Writes clears interrupt line
0x0440 0014 to 0x0440 0017 VI_BURST_REG or VI_TIMING_REG
VI video timing
(RW): [7:0] horizontal sync width in pixels
[15:8] color burst width in pixels
[19:16] vertical sync width in half lines
[29:20] start of color burst in pixels from h-sync
0x0440 0018 to 0x0440 001B VI_V_SYNC_REG
VI vertical sync
(RW): [9:0] number of half-lines per field
0x0440 001C to 0x0440 001F VI_H_SYNC_REG
VI horizontal sync
(RW): [11:0] total duration of a line in 1/4 pixel
[20:16] a 5-bit leap pattern used for PAL only (h_sync_period)
0x0440 0020 to 0x0440 0023 VI_LEAP_REG or VI_H_SYNC_LEAP_REG
VI horizontal sync leap
(RW): [11:0] identical to h_sync_period
[27:16] identical to h_sync_period
0x0440 0024 to 0x0440 0027 VI_H_START_REG or VI_H_VIDEO_REG
VI horizontal video
(RW): [9:0] end of active video in screen pixels
[25:16] start of active video in screen pixels
0x0440 0028 to 0x0440 002B VI_V_START_REG or VI_V_VIDEO_REG
VI vertical video
(RW): [9:0] end of active video in screen half-lines
[25:16] start of active video in screen half-lines
0x0440 002C to 0x0440 002F VI_V_BURST_REG
VI vertical burst
(RW): [9:0] end of color burst enable in half-lines
[25:16] start of color burst enable in half-lines
0x0440 0030 to 0x0440 0033 VI_X_SCALE_REG
VI x-scale
(RW): [11:0] 1/horizontal scale up factor (2.10 format)
[27:16] horizontal subpixel offset (2.10 format)
0x0440 0034 to 0x0440 0037 VI_Y_SCALE_REG
VI y-scale
(RW): [11:0] 1/vertical scale up factor (2.10 format)
[27:16] vertical subpixel offset (2.10 format)
0x0440 0038 to 0x044F FFFF Unused
0x0450 0000 to 0x045F FFFF Audio interface (AI) registers:
-----------------------------------------------------------
AI_BASE_REG - 0x04500000
0x0450 0000 to 0x0450 0003 AI_DRAM_ADDR_REG
AI DRAM address
(W): [23:0] starting RDRAM address (8B-aligned)
0x0450 0004 to 0x0450 0007 AI_LEN_REG
AI length
(RW): [14:0] transfer length (v1.0) - Bottom 3 bits are ignored
[17:0] transfer length (v2.0) - Bottom 3 bits are ignored
0x0450 0008 to 0x0450 000B AI_CONTROL_REG
AI control
(W): [0] DMA enable - if LSB == 1, DMA is enabled
0x0450 000C to 0x0450 000F AI_STATUS_REG
AI status
(R): [31]/[0] ai_full (addr & len buffer full)
[30] ai_busy
Note that a 1to0 transition in ai_full will set interrupt
(W): clear audio interrupt
0x0450 0010 to 0x0450 0013 AI_DACRATE_REG
AI DAC sample period register
(W): [13:0] dac rate
- vid_clock/(dperiod + 1) is the DAC sample rate
- (dperiod + 1) >= 66 * (aclockhp + 1) must be true
0x0450 0014 to 0x0450 0017 AI_BITRATE_REG
AI bit rate
(W): [3:0] bit rate (abus clock half period register - aclockhp)
- vid_clock/(2*(aclockhp + 1)) is the DAC clock rate
- The abus clock stops if aclockhp is zero
0x0450 0018 to 0x045F FFFF Unused
0x0460 0000 to 0x046F FFFF Peripheral interface (PI) registers:
----------------------------------------------------------------
PI_BASE_REG - 0x04600000
0x0460 0000 to 0x0460 0003 PI_DRAM_ADDR_REG
PI DRAM address
(RW): [23:0] starting RDRAM address
0x0460 0004 to 0x0460 0007 PI_CART_ADDR_REG
PI pbus (cartridge) address
(RW): [31:0] starting AD16 address
0x0460 0008 to 0x0460 000B PI_RD_LEN_REG
PI read length
(RW): [23:0] read data length
0x0460 000C to 0x0460 000F PI_WR_LEN_REG
PI write length
(RW): [23:0] write data length
0x0460 0010 to 0x0460 0013 PI_STATUS_REG
PI status
(R): [0] DMA busy (W): [0] reset controller
[1] IO busy (and abort current op)
[2] error [1] clear intr
0x0460 0014 to 0x0460 0017 PI_BSD_DOM1_LAT_REG or PI_DOMAIN1_REG
PI dom1 latency
(RW): [7:0] domain 1 device latency
0x0460 0018 to 0x0460 001B PI_BSD_DOM1_PWD_REG
PI dom1 pulse width
(RW): [7:0] domain 1 device R/W strobe pulse width
0x0460 001C to 0x0460 001F PI_BSD_DOM1_PGS_REG
PI dom1 page size
(RW): [3:0] domain 1 device page size
0x0460 0020 to 0x0460 0023 PI_BSD_DOM1_RLS_REG
PI dom1 release
(RW): [1:0] domain 1 device R/W release duration
0x0460 0024 to 0x0460 0027 PI_BSD_DOM2_LAT_REG or PI_DOMAIN2_REG
PI dom2 latency
(RW): [7:0] domain 2 device latency
0x0460 0028 to 0x0460 002B PI_BSD_DOM2_PWD_REG
PI dom2 pulse width
(RW): [7:0] domain 2 device R/W strobe pulse width
0x0460 002C to 0x0460 002F PI_BSD_DOM2_PGS_REG
PI dom2 page size
(RW): [3:0] domain 2 device page size
0x0460 0030 to 0x0460 0033 PI_BSD_DOM2_RLS_REG
PI dom2 release
(RW): [1:0] domain 2 device R/W release duration
0x0460 0034 to 0x046F FFFF Unused
0x0470 0000 to 0x047F FFFF RDRAM interface (RI) registers:
-----------------------------------------------------------
RI_BASE_REG - 0x04700000
0x0470 0000 to 0x0470 0003 RI_MODE_REG
RI mode
(RW): [1:0] operating mode
[2] stop T active
[3] stop R active
0x0470 0004 to 0x0470 0007 RI_CONFIG_REG
RI config
(RW): [5:0] current control input
[6] current control enable
0x0470 0008 to 0x0470 000B RI_CURRENT_LOAD_REG
RI current load
(W): [] any write updates current control register
0x0470 000C to 0x0470 000F RI_SELECT_REG
RI select
(RW): [2:0] receive select
[2:0] transmit select
0x0470 0010 to 0x0470 0013 RI_REFRESH_REG or RI_COUNT_REG
RI refresh
(RW): [7:0] clean refresh delay
[15:8] dirty refresh delay
[16] refresh bank
[17] refresh enable
[18] refresh optimize
0x0470 0014 to 0x0470 0017 RI_LATENCY_REG
RI latency
(RW): [3:0] DMA latency/overlap
0x0470 0018 to 0x0470 001B RI_RERROR_REG
RI error
(R): [0] nack error
[1] ack error
0x0470 001C to 0x0470 001F RI_WERROR_REG
RI error
(W): [] any write clears all error bits
0x0470 0020 to 0x047F FFFF Unused
0x0480 0000 to 0x048F FFFF Serial interface (SI) registers:
------------------------------------------------------------
SI_BASE_REG - 0x04800000
0x0480 0000 to 0x0480 0003 SI_DRAM_ADDR_REG
SI DRAM address
(R/W): [23:0] starting RDRAM address
0x0480 0004 to 0x0480 0007 SI_PIF_ADDR_RD64B_REG
SI address read 64B
(W): [] any write causes a 64B DMA write
0x0480 0008 to 0x0480 000B Reserved
0x0480 000C to 0x0480 000F Reserved
0x0480 0010 to 0x0480 0013 SI_PIF_ADDR_WR64B_REG
SI address write 64B
(W): [] any write causes a 64B DMA read
0x0480 0014 to 0x0480 0017 Reserved
0x0480 0018 to 0x0480 001B SI_STATUS_REG
SI status
(W): [] any write clears interrupt
(R): [0] DMA busy
[1] IO read busy
[2] reserved
[3] DMA error
[12] interrupt
0x0480 001C to 0x048F FFFF Unused
Unused:
-------
0x0490 0000 to 0x04FF FFFF Unused
Cartridge Domain 2(Address 1):
------------------------------
0x0500 0000 to 0x05FF FFFF Cartridge Domain 2
0x0500 0508 - some roms read from this address.
SRAM could be here
Cartridge Domain 1(Address 1):
------------------------------
0x0600 0000 to 0x07FF FFFF Cartridge Domain 1
This address seems to be where
the n64ddrive would be addressed
0x0800 0000 to 0x0FFF FFFF Cartridge Domain 2
SRAM could be here
Cartridge Domain 1(Address 2):
------------------------------
0x1000 0000 to 0x1000 003F ROM header:
---------------------------------------
0x1000 0000 initial PI_BSB_DOM1_LAT_REG value
0x1000 0001 initial PI_BSB_DOM1_PGS_REG value
0x1000 0002 initial PI_BSB_DOM1_PWD_REG value
0x1000 0003 initial PI_BSB_DOM1_PGS_REG value
0x1000 0004 to 0x1000 0007 Clock Rate
0x1000 0008 to 0x1000 000B Boot address offset
0x1000 000C to 0x1000 000F Release offset
0x1000 0010 to 0x1000 0013 CRC1
0x1000 0014 to 0x1000 0017 CRC2
0x1000 0018 to 0x1000 001F Unused
0x1000 0020 to 0x1000 0033 Image name
0x1000 0034 to 0x1000 003A Unused
0x1000 003B Manufacturer ID
0x1000 003C to 0x1000 003D Cartridge ID
0x1000 003E Country code
0x1000 003F Unused
0x1000 0040 to 0x1000 0B6F RAMROM_BOOTSTRAP_OFFSET
0x1000 0B70 to 0x1000 0FEF RAMROM_FONTDATA_OFFSET
0x1000 0FF0 to 0x1000 0FFF Unused
0x1000 1000 to 0x10FF 9FFF RAMROM_GAME_OFFSET
0x10FF A000 to 0x10FF AFFF RAMROM_APP_READ_ADDR
0x10FF B000 to 0x10FF BFFF RAMROM_APP_WRITE_ADDR
0x10FF C000 to 0x10FF CFFF RAMROM_RMON_READ_ADDR
0x10FF D000 to 0x10FF DFFF RAMROM_RMON_WRITE_ADDR
0x10FF E000 to 0x10FF EFFF RAMROM_PRINTF_ADDR
0x10FF F000 to 0x10FF FFFF RAMROM_LOG_ADDR
0x1100 0000 to 0x17FF FFFF Unused
0x1800 0000 to 0x1800 0003 GIO Interrupt Register (R)
0x1800 0004 to 0x1800 03FF Unused
0x1800 0400 to 0x1800 0403 GIO Sync Register (R/W)
0x1800 0404 to 0x1800 07FF Unused
0x1800 0800 to 0x1800 0803 Cartridge interrupt Register (R)
0x1800 0804 to 0x1F39 FFFF Unused
PIF Boot ROM:
-------------
0x1FC0 0000 PIF_ROM_START
0x1FC0 07BF PIF_ROM_END
PIF (JoyChannel) RAM:
---------------------
0x1FC0 07C0 PIF_RAM_START
0x1FC0 07C4 (16 low bits) Status of controller:
%X X X X X X X X X X X X X X X X
A B Z ST U D L R ? ? PL PR CU CD CL CR
A,B,Z,ST = A,B,Z, Start buttons
U,D,L,R = Joypad directions
?,? = Unknown
PL,PR = Pan left, Pan right buttons
CU,CD,CL,CR = C buttons (up,down,left,right)
0x1FC0 07FF PIF_RAM_END
Reserved:
---------
0x1FC0 0800 to 0x1FCF FFFF Reserved
Cartridge Domain 1(Address 3):
------------------------------
0x1FD0 0000 to 0x7FFF FFFF Unknown
0x8000 0000 to 0xffff ffff external SysAD device
-------------------------------------------------
0x8000 0000 to 0x9FFF FFFF kseg0 (Mirror of 0x0000 0000 to 0x1FFF FFFF)
0xA000 0000 to 0xBFFF FFFF kseg1 (Mirror of 0x0000 0000 to 0x1FFF FFFF)
0xC000 0000 to 0xDFFF FFFF ksseg (TLB mapped)
0xE000 0000 to 0xFFFF FFFF kseg3 (TLB mapped)
rcp
Note: This document contains some errors, please refer to n64ops#f.txt,
n64ops#g.txt for information about the RSP opcodes, and n64ops#c.txt
for the opcode matrix. /anarko
=============================================================================
RCP Technical Information - v1.0
=============================================================================
Overview
--------
This is the file which I am sure many a N64 emu programmer has been waiting
for. I know I wanted it when I started but I had to compile this document
myself.
Please Note: This information is a compilation from many sources and it is
possible that some of this may or may not be correct. However, I have
endevoured to make sure that it is as accurate as possible.
This document is also incomplete so I will be adding more information in
future releases.
So what is included in this document:
* RSP Overview
* RCP Opcode Encoding
* RCP Vector Instruction Set
RSP Overview
------------
The RSP instruction set is essentially a 32-Bit subset of the MIPS R4000
instruction set, with some extensions. Instructions which are not
implemented include:
* Any 64-bit Instruction
* Mulitplies
* Divides
* Branch Likely
* Most System Control Opcodes
The RSP Vector Unit (VU) is implemented as a MIPS Coprocessor (COP2),
with the machine language conforming to the MIPS Coprocessor definition.
The RSP assembler uses a mnemonic syntax for each VU instruction.
The RSP Registers are as follows:
* 32 x 32 bit Scalar Registers (Normal MIPS set).
* 32 Vector Registers, each with 8 x 16 bit entries.
* No Scalar Multiplies or HI/LO registers.
* 8 Vector ALUs. Each ALU appears to have a 'hidden' 32 bit accumulator
and hidden flags registers.
The RSP can only address it's 4K IMEM and 4K DMEM, everything else has to
be done via DMA. The RCP DMA control registers are mapped to COP0
registers.
RSP Memory is as follows:
* RSP DMEM Start 0x04000000
* RSP DMEM End 0x04000FFF
* RSP IMEM Start 0x04001000
* RSP IMEM End 0x04001FFF
The MUL/MAC instructions do 16 x 16 -> 32 and combine this with the hidden
accumulator in various ways. The upshot is that it is possible to do
32 x 32 -> 32 multiplies in the following four instructions:
* VMUDL
* VMADM
* VMADN
* VMADH
The COP2 control registers appear to be vector ALU flags, bit per element.
(VCO, VCC, VCE)
The vector opcodes are all 3 operand, and the second source can have a
modifier allowing elements to be replicated in various ways:
Instruction Elements of $v3 sent to ALUs
vadd $v1, $v2, $v3 0 1 2 3 4 5 6 7
vadd $v1, $v2, $v3[0q] 0 1 2 3 0 1 2 3
vadd $v1, $v2, $v3[1q] 4 5 6 7 4 5 6 7
vadd $v1, $v2, $v3[0h] 0 1 0 1 0 1 0 1
vadd $v1, $v2, $v3[1h] 2 3 2 3 2 3 2 3
vadd $v1, $v2, $v3[2h] 4 5 4 5 4 5 4 5
vadd $v1, $v2, $v3[3h] 6 7 6 7 6 7 6 7
vadd $v1, $v2, $v3[0] 0 0 0 0 0 0 0 0
vadd $v1, $v2, $v3[1] 1 1 1 1 1 1 1 1
vadd $v1, $v2, $v3[2] 2 2 2 2 2 2 2 2
vadd $v1, $v2, $v3[3] 3 3 3 3 3 3 3 3
vadd $v1, $v2, $v3[4] 4 4 4 4 4 4 4 4
vadd $v1, $v2, $v3[5] 5 5 5 5 5 5 5 5
vadd $v1, $v2, $v3[6] 6 6 6 6 6 6 6 6
vadd $v1, $v2, $v3[7] 7 7 7 7 7 7 7 7
Loads and stores can access byte, short, word, double word or quad word.
For sizes less than quad word, the offset in the vector regsiter can be
selected (on boundaries of that size). There are a whole bunch of 'fancy'
loads and store which appear to shuffle the data on the way in out in
useful ways. The offset for vector loads and vector stores is scaled
depending on the element size.
The 'guess' instructions (VRCP?, VRSQ?) are pipelined - result is derived
from the previous instructions.
With some of the Vector Multiply Instructions the Accumlator is a hidden
32 bit accumulator per element.
* VMUDL: acc = (src1 * src2) >> 16, dest = acc & 0xffff
* VMADL: acc += (src1 * src2) >> 16, dest = acc & 0xffff
* VMUDM: acc = (src1 * src2), dest = acc >> 16
* VMADM: acc += (src1 * src2), dest = acc >> 16
* VMUDN: acc = (src1 * src2), dest = acc & 0xffff
* VMADN: acc += (src1 * src2), dest = acc & 0xffff
* VMUDH: acc = (src1 * src2) >> 16, dest = acc >> 16
* VMADH: acc += (src1 * src2) >> 16, dest = acc >> 16
RCP Opcode Encoding
-------------------
This section is still in it's preliminary stages.
R-Type (Register) Instruction Format
+-----------+---------+-------+-------+-------+-----------+
| OP | RS | RT | RD | SA | Funct |
+-----------+---------+-------+-------+-------+-----------+
| 010010 | 10000 | ????? | ????? | ????? | ?????? |
| | | | | | |
| CP2 Instr | Sub OpC | VReg3 | VReg2 | VReg1 | CP2 Funct |
+-----------+---------+-------+-------+-------+-----------+
2..0 COP2 Function
0 1 2 3 4 5 6 7
5..3 +-------+-------+-------+-------+-------+-------+-------+-------+
0 | VMULF | VMULU | VRNDP | VMULQ | VMUDL | VMUDM | VMUDN | VMUDH |
+-------+-------+-------+-------+-------+-------+-------+-------+
1 | VMACF | VMACU | VRNDN | VMACQ | VMADL | VMADM | VMADN | VMADH |
+-------+-------+-------+-------+-------+-------+-------+-------+
2 | VADD | VSUB | VSUT | VABS | VADDC | VSUBC | VADDB | VSUBB |
+-------+-------+-------+-------+-------+-------+-------+-------+
3 | VACCB | VSUCB | VSAD | VSAC | VSUM | VSAW | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
4 | VLT | VEQ | VNE | VGE | VCL | VCH | VCR | VMRG |
+-------+-------+-------+-------+-------+-------+-------+-------+
5 | VAND | VNAND | VOR | VNOR | VNXOR | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
6 | | | | | | | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
7 | VEXTT | VEXTQ | VEXTN | VINST | VINSQ | VINSN | | |
+-------+-------+-------+-------+-------+-------+-------+-------+
RCP Vector Instruction Set
--------------------------
This section is still in it's preliminary stages. I have a lot more
information about each instruction but have not had the time to write it
all up yet.
VMULF Vector (Frac) Multiply
VMACF Vector (Frac) Multiply Accumulate
VMULU Vector (Unsigned Frac) Multiply
VMACU Vector (Unsigned Frac) Multiply Accumulate
VRNDP Vector DCT Round (+)
VRNDN Vector DCT Round (-)
VMULQ Vector (Integer) Multiply
VMACQ Vector (Integer) Multiply Accumulate
VMUDH Vector (High) Multiply
VMADH Vector (High) Multiply Accumulate
VMUDM Vector (Mid-M) Multiply
VMADM Vector (Mid-M) Multiply Accumulate
VMUDN Vector (Mid-N) Multiply
VMADN Vector (Mid-N) Multiply Accumulate
VMUDL Vector (Low) Multiply
VMADL Vector (Low) Multiply Accumulate
VADD Vector Add
VSUB Vector Subtract
VSUT Vector SUT (vt - vs)
VABS Vector Absolute Value
VADDC Vector ADDC
VSUBC Vector SUBC
VADDB Vector Add Byte
VSUBB Vector Subtract Byte
VACCB Vector Add Byte/Add Accumulator
VSUCB Vector Subtract Byte/Add Accumulator
VSAD Vector SAD
VSAC Vector SAC
VSUM Vector SUM
VSAW Vector SAW
VLT Vector Less Than
VEQ Vector Equal To
VNE Vector Not Equal To
VGE Vector Greater Than or Equal To
VCL Vector Clip Low
VCH Vector Clip High
VCR Vector, 1's Complement Clip
VMRG Vector Merge
VAND Vector Logical AND
VNAND Vector Logical NAND
VOR Vector Logical OR
VNOR Vector Logical NOR
VXOR Vector Logical Exclusive OR
VNXOR Vector Logical NOT Exclusive OR
VNOOP Vector No-Operation
VMOV Vector Scalar-Element Move
VRCP Single Precision, Lookup Source, Write Result
VRSQ Single Precision, Lookup Source, Write Result
VRCPH Set Source, Write Previous Result
VRSQH Set Source, Write Previous Result
VRCPL Lookup Source and Previous, Write Result
VRSQL Lookup Source and Previous, Write Result
VINST Vector Insert Triple (5/5/5/1)
VEXTT Vector Extract Triple (5/5/5/1)
VINSQ Vector Insert Quad (4/4/4/4)
VEXTQ Vector Extract Quad (4/4/4/4)
VINSN Vector Insert Nibble (4/4/4/4) Sign-Extended
VEXTN Vector Insert Nibble (4/4/4/4) Sign-Extended
LBV Load Byte into Vector
LSV Load Short into Vector
LLV Load Word into Vector
LDV Load Doubleword into Vector
LQV Load Quadword into Vector
LRV Load Rest Vector
LPV Load Packed Vector
LUV Load Unpack Vector
LHV Load Half Vector
LFV Load Fourth Vector
LWV Load Wrap Vector
LTV Load Transpose Vector
SBV Store Byte from Vector
SSV Store Short from Vector
SLV Store Word from Vector
SDV Store Doubleword from Vector
SQV Store Quadword from Vector
SRV Store Rest Vector
SPV Store Packed Vector
SUV Store Unpack Vector
SHV Store Half Vector
SFV Store Fourth Vector
SWV Store Wrap Vector
STV Store Transpose Vector
I have not included the standard MIPS opcodes used in the RCP.
sound
heres how one way to make sound on N64 :
Crazy nation trainer (xtremeG version)
[we tested button and its time to make sound!]
lui $t4,8031 ;make pointer to 'yes' sound
addiu $t4,$t4,4F10 ;80314f10 = start
addiu $t5,$zero,4A71 ;4A71=length
addiu $t6,$zero,1388 ;1388= DAC rate
addiu $t7,$zero,0001 ;1=BIT rate
jal here
nop
[draw yes]
......
[we tested button and time to make 'no' sound]
lui $t4,8031 ;make pointer to 'no' sound
addiu $t4,$t4,12C4 ;803112C4
addiu $t5,$zero,3C45 ;3C45=length
addiu $t6,$zero,1388 ;DAC rate
addiu $t7,$zero,0001 ;1=BIT rate
jal here
nop
[draw no]
.....
[...initialize vid, audio]
addiu $t4,$zero,0000 ;[blank out sound]
addiu $t5,$zero,0000 ;initialize
addiu $t6,$zero,0001
addiu $t7,$zero,0001
here: lui $t8,A450
sw $t4,0000($t8) ;start RDRAM address
sw $t5,0004($t8) ;length
addiu $t9,$zero,0001
sw $t9,0008($t8) ;1 = enable dma
sw $t6,0010($t8) ;dac rate
sw $t7,0014($t8) ;bit rate
jr $ra
nop
controll
This file contains information from Titanik and Niki W. Waibel,
i have not put it together, but the info is just copied from e-mails from
them both.
--------------------------------------------------------------------------
Titanik:
--------------------------------------------------------------------------
Those routines are a RIP of the code from TITANIK/CrazyNation,
it's the not way the "normal" games read the joypad.
You first have to set 2 places in memory that contains 64 bytes of
certain values, lets call them pif1 and pif2.
they contain the values :
pif1: DW $FF010401
DW $00000000
DW $FF010401
DW $00000000
DW $FF010401
DW $00000000
DW $FF010401
DW $00000000
DW $FE000000
DW $00000000
DW $00000000
DW $00000000
DW $00000000
DW $00000000
DW $00000000
DW $00000001
pif2: DW 0,0,0,0,0,0,0,0 ;by words we mean 32bits!
DW 0,0,0,0,0,0,0,0 ;I think this is 64 bytes..
You need to initialize this register before starting (your program will
run few a few seconds then die if not done)
addiu t0,r0,8
lui at,$BFC0
sw t0,$07FC(at) ;CLEAR BUTTONS
move #8,$BFC007FC
now when you start your program and begin your main loop the begginning
of the loop should begin with (if you want to read joysticks):
START:
lui t2,$0031 ;t2 = if org is 80310000 then $0031
; if org is 80200000 then $0020
;I myself am still confused bout
;how ram is mirrored in the system
;but this is how it is
ori t2,t2,pif1 ;lower 16 bits pointer to pif1
lui at,$A480 ;SI DRAM ADDR. at=$A4800000
sw t2,$0000(at) ; pif1
lui t2,$1FC0
ori t2,t2,$07C0 ;t2=$1fc007c0
lui at,$A480
sw t2,$0010(at) ;64B DRAM -> PIF ;poke them thar
;registers arrrrr
[...do your stuff in here, then when ready to
loop back do this to test josticks...]
lui t2,$0031 ;look familiar
ori t2,t2,pif2
lui at,$A480 ;SI DRAM ADDR
sw t2,$0000(at) ;$31pif2
lui t2,$1FC0
ori t2,t2,$07C0 ;PIF joychannel
lui at,$A480
sw t2,$0004(at) ;64B PIF->DRAM ;peek values to dram ? i
;guess this is necassary
lui t1,$BFC0
lbu t1,$07FF(t1) ;BYTE(JOY)-T1 ;for some reason this
;is done but I dont know why!
lui t0,$BFC0 ;the value is disregarded
lhu t0,$07C4(t0) ;**HWORD(JOY)->T0**
nop
beq t0,r0,START ;***we have our joystick value in t0***
nop ;if no buttons mashed then start over
andi t1,t0,$4000 ;each bit represents a button so
;start testing them
beq t1,r0,next1 ;I used to know what each bit represented
; (what button) but I lost the info
nop ;andi $4000 /$8000 A/B $100/$200 left/right etc...
; I think this is right I
[routine] ;might have it backwords or somethin
next1: etc.. etc..
;there are a couple of bits that i
;dont know what they do.
;havent figured out where the
;analog joy data is.
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
From: Ben Stembridge <stembbe@mail.auburn.edu>
To: anarko <anarko@flashback.net>
Subject: some stuff for n64ops#E
--------------------------------------------------------------------------------
at 0x1FC0 07C4 - 07c5 is the status of the controller, each bit is 1 when
the button is mashed, 0 otherwise.
07C4 (HALFWORD-16 BITS) = STATUS OF CONTROLLER
%X X X X X X X X X X X X X X X X
A B Z ST U D L R ? ? PL PR CU CD CL CR
A,B,Z =BUTTONS
ST = START
U,D,L,R = JOYPAD
?,? = UNKNOWN
PL,PR = PAN LEFT , PAN RIGHT BUTTONS
CU,CD,CL,CR = C BUTTONS |UP,DOWN,LEFT,RIGHT
Ben Stembridge
Mech. ENG.
Auburn University
stembbe@mail.auburn.edu
--------------------------------------------------------------------------
Niki W. Waibel:
--------------------------------------------------------------------------
additional controller info:
init controller:
rdram -> pif
ff010300
ffffffff ... for each controller
fe000000 ... at the end (after controller 4)
than pif ram is set to:
????EE??
TTTTSS?? ... for each controller
?? ... ? zero (0x00)
EE ... error field
0x80: no response (no controller connected)
0x40: Overrun error (?)
0x00: no error (controller connected)
TTTT
... type field
0x0001 absolute
0x0002 relative
0x0004 joyport
0x8000 eeprom !!!
SS ... status field
0x01 card on
0x02 card pull
0x04 addr crc err
0x80 eeprom busy
get controller data:
rdram -> pif
ff010400
ffffffff ... for each controller
fe000000 ... at the end (after controller 4)
than pif ram is set to (!!!attention!!! pif ram is actualized every read):
0xbfc007c0: ????EE??
0xbfc007c4: BBBBXXYY
0xbfc007c8: |
0xbfc007cc: |_same as above but for controller 2
...
BBBB ... buttons (you have that in controll.txt)
XX ... stick x pos [-128..127] or 0x80 (left) .. 0x00 (middle) .. 0x7f (right)
YY ... stick y pos [-128..127] or 0x80 (down) .. 0x00 (middle) .. 0x7f (up)
!!!attention!!!
all pur versions seem NOT to have implemented the SIGNED XX and YY bytes
correct.
0x80 0x81 0x82 ... 0xff 0x00 0x01 .. 0x7c 0x7e 0x7f
-128 -127 -126 -1 0 1 125 126 127
left pos middle pos right pos
down pos middle pos up pos
!!!attention!!!
