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Macrovision eliminator v2.3 operational description
Macrovision eliminator v2.3 operational description
===================================================
Note: this document assumes that you are familiar with the Macrovision FAQ.
Analog section:
---------------
The composite video signal enters the circuit via CON2. It is then
terminated with the nominal impedance of 75 by R6. The average DC level is
then raised to approx. 0.5V+ (V+ = positive supply) [C13,R4,R5], because
that means a symmetrical power supply is avoided by moving the signal to
the optimal operating range of the components. Next the video enters one of
the electronic switches in 4053 [IC1A]. This switch is driven so that it
chooses the black level during protection pulses and normal video otherwise
(VIDEO/BLACK switch for future reference).
The unprotected video is then lead to the output buffer, which consists of
two emitter followers in series. A simple one-transistor buffer is not
always adequate, because the changes in the impedance the output sees can
affect the preceeding circuits. This buffer insulates its input and output
very effectively. Finally the DC-offset is removed from the output [C12]
and the signal exits the circuit via CON1.
The black level which replaces the protection is determined by the sample
and hold circuit [IC7,IC1 B,C1,C3]. The video signal enters the operational
amplifier IC7A, which is used as a unity-gain buffer. This op-amp is
sufficiently fast to allow the video signal through, yet quite cheap. The
electronic switch IC1B then performs the sampling action. The signal is
allowed through to the hold capacitor C1, when the BACK PORCH signal is
high. The back porch is a small period after each horizontal
synchronization pulse, see picure below:
This is one normal PAL/NTSC scanline as seen on an oscilloscope screen.
Time in microseconds
0 1 2 3 4 5 6 0 1
0123456789012345678901234567890123456789012345678901234567890123012345678901
___________________________________________________ ______
| ^-- White level | |
| | Color |
| Arbitrary picture data | burst--v |
| | |
_MM_|___________________________________________________|_ _MM_|______
| WW ^-- Black level | | WW
| |____|
Front porch --^ ^ ^-- Back
Horizontal | porch
synchronization --+
The colour burst also occupies most of the back porch, but the average
level of the whole period can be taken as the black level. The BACK PORCH
signal is only active after real horizontal sync pulse, not after false
Macrovision pulses. To make things doubly sure, the video is taken after
the VIDEO/BLACK switch, which would also allow sampling at false pulses,
because the circuit would only sample its own output. This is also
essential when deprotecting the lower region, because there the DC level of
the back porch has been raised to super-white, which must not be mistakenly
sampled as black.
The captured black level in the hold capacitor C1 is amplified by the op-amp
IC7B. Capacitor C3 at the output removes a glitch that results from
switching transients in the 4053.
Mixed analog-digital section (i.e. the sync separator)
------------------------------------------------------
The synchronization separator section of the circuit is a mix of digital
and analog processing, which can only be realized because of the special
properties of the CMOS gates. The analog operation depends on the
nonlinearity of a CMOS gate: if the input level is near either supply
voltage, the gain is relatively small, but at 0.5V+ the gain is
ernomous. Graphically the relationship would look like this:
input CMOS buffer output
___ ____
/ /
/ |\ |
/ --| >-- |
/ |/ |
__ ___
To the circuit: the video signal enters the sync separator through the
decoupling capacitor C9. It is then applied to the input of a CMOS inverter
IC6A, which is biased so that the synchronization pulses are in the middle
of the high-gain area. The gate then amplifies and distorts the signal so
that the sync pulses are at digital levels. The gate is biased like this:
if there is no signal, resistor R10 keeps the input at 0.5V+. If then a
video signal is applied, the tips of the sync pulses go through diodes D20
and D21 and resistor R11, increasing the voltage at the input of IC6A
until Vout-Vin is less than the two diode drops (~1.5v). This level is just
right for sync pulses hitting the "big gain" area. R10 tries slowly to move
the circuit out of this state, but it does not succeed as long as the sync
pulses keep coming.
The next inverter [IC6B] then cleans and amplifies the final signal which
is called /COMPOSITE SYNC. VERTICAL SYNC can be extracted from it simply by
low-pass filtering. The vertical sync period is depicted below:
________ _ _ _ _ _ _ _ _ __________ ___ +V /COMPOSITE
| | | | | | | | | | | | | | | | | | | | | | | SYNC
| | | | | | | | |_|_|_|_|_| | | | | | | | | | ___ 0V
_________ ___ +V VERTICAL
| | SYNC
________________| |__________________ ___ 0V
As can be seen, the average level of the composite sync signal falls at
vertical sync period. Resistor R12 and capacitor C10 form a low-pass
filter, whose output is buffered and the edges sharpened by the following
inverter [IC6C].
The signal /BACK PORCH CANDIDATE is extracted from the composite sync by
starting an RC-timer at every rising edge. The timing is chosen so that the
output of the following gate is logic low during the alledged back-porch
period. This timer works like this: capacitor C11 derives every edge from
the sync signal. The diode (D22) shorts every falling edge to ground, but
resistors R13 and R14 determine how fast the voltage falls after a rising
edge. This defines the length of the output pulse from the inverter acting
as the output buffer [IC6D].
The /BACK PORCH CANDIDATE then activates a timer that approximately
determines the active or visible portion of a line. It is used for getting
rid of the false synchronization pulses Macrovision has. The timer, built
around C2, R19 and D47, works like the /BACK PORCH CANDIDATE timer, but
this time the negative going edge is the trigger. The output is then used
as feedback for preventing the retriggering of the very same timer. This is
accomplished by diodes D34 and D35 and resistor R18, which comprise a
wired-OR gate at the input of IC6E. If the timer is active, meaning its
output is high, no pulses coming to the input of D34 can reach and
retrigger the timer. This circuit produces both the BACK PORCH and VISIBLE
signals, tapped from before and after the line timer, respectively. They
are cascaded so that the end of BACK PORCH starts the VISIBLE period.
Digital section
---------------
The explanation of the workings of the digital section is best started from
the line counter IC5, which is a 12-bit ripple counter. The counter does
not have to be synchronous because the outputs are latched after a very
long settling time. The counter is reset by VERTICAL SYNC at the beginning
of each field and it is incremented at every line where VERTICAL SYNC is
inactive. Nine bits are sufficient for addressing every line of each field
(from 0 to approx. 310). The clock signal has to be a line-frequency pulse
that is not affected by the Macrovision false synchronization, otherwise
the protection pulses would advance the count, too. The VISIBLE signal is
used here, but the BACK PORCH signal would work as well.
The current line is now always available at the output pins of the
counter. The four 9-bit diode-jumper-arrays are wire-AND gates that are
used for selecting the lines wanted. Each of those selectors works by
ANDing all the '1'-bits from the binary representation of the chosen
line. Because the counter always counts upwards from 0, we can deduce after
some thinking that the first line that causes the output of the selector to
go active is always the wanted line. But there is one problem: only the
first match is true, every other match after that is false. The output
cannot therefore be used directly, but instead it drives a two-state state
machine consisting of one J-K flip-flop. The flip-flop is reset at the same
time as the counter. If the desired line has not been reached the Q output
is 0, but during the line and afterwards Q is 1. The first (and correct)
pulse from the selector changes the state of the flip-flop, but the
subsequent (false) ones do not.
After this preliminary work it is quite straightforward to define regions
of lines. Each region can be defined by its start and end lines, which
imply two selector state-machines. The start line Q and end line /Q outputs
are the ANDed (in the circuit with wire-ANDs) and the output is active at
lines start..end-1. The signal in this circuit created this way is UPPER
AREA, which defines where the main above-the-picture protection area
resides. The LOWER AREA signal, which defines where the auxiliary
below-the-picture protection area resides, needs only the starting line,
because the lower area ends when vertical sync begins. It is therefore not
necessary to keep a separate selector for it, because the VERTICAL SYNC
signal resets the startline flip-flop at the correct time anyway.
The knowledge of only the regions is not enough for removing the
protection, though, because sub-line information is needed. This is
provided by the laboriously generated VISIBLE and BACK PORCH signals. The
protection in the upper area consists of false synchronization pulses in
the active or visible portion of the lines. Thus the correct logical
function would be to substitute the video with black when UPPER AREA _and_
VISIBLE are active. This is actually the function of the NAND-gate IC2B,
which produces the /UPPER PROTECT signal as the result. In the lower area
the back porch voltage level has been from black to super-white. To remedy
this, the /LOWER PROTECT signal must be generated with the function LOWER
AREA _and_ BACK PORCH, implemented with the NAND-gate IC2C.
The only thing left now is to make sure that either one of these PROTECT
signals causes the substitution of video with black. Because they are both
active low, the needed logical OR is transformed by DeMorgan to an actual
AND-gate. This function is performed by IC2A, which produces the PROTECT
signal that drives the video/black switch IC1A.
Timings and waveforms
---------------------
Below are some graphs of the intended relationships of the signals:
normal video line
___________________________________________________
| |
| |
| |
| |
_ _MM_|___________________________________________________|_ _MM_
| | WW | | WW
|____| |____|
protected line in upper area
_ _ _ _ _ _ _
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
| | | | | | | | | | | | | |
_ _MM__ | | | | | | | | | | | | | |__________________ _MM_
| | WW | | | | | | | | | | | | | | | | WW
|____| |_| |_| |_| |_| |_| |_| |_| |____|
protected line in lower area
_MM_
| WW |___________________________________________________
| | |
| | |
| | |
| | |
_ | |___________________________________________________|_ _MM_
| | | | WW
|____| |____|
/COMPOSITE SYNC during normal line and lower area protection
_ __________________________________________________________ ___
| | | |
|____| |____|
/COMPOSITE SYNC during upper area protection
_ _____ __ __ __ __ __ __ ____________________ ___
| | | | | | | | | | | | | | | | | |
|____| |_| |_| |_| |_| |_| |_| |_| |____|
/BACK PORCH CANDIDATE during normal line and lower area protection
______ _________________________________________________________
| | |
|_____| |___
/BACK PORCH CANDIDATE during upper area protection
______ _ _ _ _ _ _ _ ___________________
| | | | | | | | | | | | | | | | |
|_____| |__| |__| |__| |__| |__| |__| |_____| |___
BACK PORCH at all times
_____ ___
| | |
______| |_________________________________________________________|
VISIBLE at all times
__________________________________________________
| |
____________| |__________
Now a change of scale. The figures above illsutrate the workings during one
line. The following depicts the signals over a field. The noninteresting
part (picture) at the middle has been cut out.
VERTICAL SYNC
_______ _______
| | | |
__| |_____________________________________...______________| |
UPPER AREA START
__ __________________________...______________
| | |
|__________________| |________
/UPPER AREA END
__________________________________________ ________
| | |
__| |__...______________|
UPPER AREA
_______________________ ________
| | |
_____________________| |__...______________|
LOWER AREA
__ ___________
| | |
|_____________________________________________...__| |________
/UPPER PROTECT
_____________________ __..._______________________
| | | | | | | | | | | | |
|_|_|_|_|_|_|_|_|_|_|_|_|
/LOWER PROTECT
________________________________________________...__ _ _ _ _ _ _ ________
| | | | | | |
| | | | | | |
PROTECT
_ _ _ _ _ _ _ _ _ _ _ _
| | | | | | | | | | | | | | | | | | | |
_____________________| | | | | | | | | | | | |__...__|_|_|_|_|_|_|________
--
Hopefully there are no mistakes in this list, but
I still do not guarantee anything :-)
IC1 4053 CMOS triple analog switch
IC2 4011 CMOS 4*NAND
IC3 4027 CMOS dual J-K flip-flop
IC4 4040 CMOS 12-bit ripple counter
IC5 4528 CMOS dual monostable
IC6 4069 CMOS 6*NOT
IC7 TL082 JFET operational amplifier
T1 BC548 small-signal NPN transistor
T2 BC558 small-signal PNP transistor
D1..
D18
D20..
D22 1N4148 * 21 small-signal diodes
D19 1N4001 power diode
J1..
J18 jumper * 18 jumper blocks or suitably wired numerical switches
R9 10
R6 75
R1,R2 100 * 2
R11 1.5k
R3 2.2k
R13 6.8k
R14 22k
R12 33k
R4,R5,
R7,R8 68k * 4
R10 470k
R15 100k trimmer
C11 220pF
C10 470pF
C2 2.2nF
C3..
C9 100nF * 7
C1 0.22uF
C13 15uF
C12 220uF
C14 470uF
CON1 RCA female or other suitable video connector
CON2 RCA female or other suitable video connector
CON3 some suitable power connector
--
