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Guide to the PowerVR-chip of the Dreamcast
The PowerVR-chip of the Dreamcast.
Guide to the PowerVR-chip of the Dreamcast
by Lars Olsson
v0.40, 2001-Aug-18
a05f8000: (id)
+------+
| 31-0 |
| id |
+------+
id:
0x17fd11db: Set5.xx development box or consumer machine
others: Set4 delopment box or others
a05f8004: (revision)
+----------------------+
| 31-8 | 7-4 | 3-0 |
| n/a | major | minor |
+----------------------+
major.minor:
0.1: Set5.16 development box (?)
>= 1.1: Set5.2x development box or consumer machine
a05f8008: (reset)
+---------------------------------+
| 31-3 | 2 | 1 | 0 |
| n/a | buss | render | transfer |
+---------------------------------+
bus:
0: normal
1: reset VRAM bus
render:
0: normal
1: reset rendering
transfer:
0: normal
1: reset registration
a05f8014: (startrender)
+-------+
| 31-0 |
| start |
+-------+
start:
Write 0xffffffff to initiate rendering sequence.
a05f8018:
+------+
| 31-0 |
| ??? |
+------+
a05f8020: (ob_addr)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Location of the Object Buffer in VRAM (64-bit aligned) to be
used when the PVR is rendering a scene
a05f802c: (tilebuf_addr)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Location of the Tile Buffer in VRAM (64-bit aligned) to be
used when the PVR is rendering a scene.
a05f8030: (spansort_cfg)
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x00000101 for now.
a05f8040: (border_col)
+--------------+
| 31-24 | 23-0 |
| n/a | col |
+--------------+
col:
Border colour in RGB888-format.
a05f8044: (fb_cfg1)
+---------------------------------------------------------------
| 31-24 | 23 | 22 | 21-16 | 15-8 | 7 | 6-4 |
| n/a | clock | ??? (0) | ??? (0) | ??? (0) | n/a | ??? (0) |
+---------------------------------------------------------------
----------------------------------+
| 3-2 | 1 | 0 |
| pixelmode | linedouble | enable |
----------------------------------+
clock:
0: normal
1: pixel-clock runs at twice the speed (for VGA-mode)
pixelmode: (alphamode is not set)
0: ARGB1555 (2 bytes/pixel)
1: RGB565 (2 bytes/pixel)
2: RGB888 (3 bytes/pixel)
3: ARGB8888 (4 bytes/pixel)
linedouble:
0: normal
1: scan lines are sent twice (for 240 scanlines in VGA-mode)
enable:
0: disable display
1: enable display
a05f8048: (fb_cfg2)
+----------------------------------------------------------+
| 31-24 | 23-16 | 15-8 | 7-4 | 3 | 2-0 |
| n/a | threshold | ??? (0) | n/a | dither | render mode |
+----------------------------------------------------------+
threshold:
threshold for alpha transparency
dither:
0: dither disabled
1: dither enabled for 2 bytes/pixel displays
render mode:
0: RGB555
1: RGB565
2: ARGB4444
3: ARGB1555
4: RGB888
5: 0RGB8888
6: ARGB8888
7: ARGB4444
a05f804c: (render modulo)
+---------------+
| 31-9 | 8-0 |
| n/a | modulo |
+---------------+
(haven't got this to work in *RGB888 modes...)
modulo:
((bytes/pixel * width)/8
a05f8050: (display_addr1)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Address in VRAM for displaying odd lines.
a05f8054: (display_addr2)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Address in VRAM for displaying even lines.
a05f805c: (display_size)
+---------------------------------+
| 31-30 | 29-20 | 19-10 | 9-0 |
| n/a | modulo | height | width |
+---------------------------------+
modulo:
Number of words in VRAM before next scanline starts, plus 1
height:
interlace: height/2 - 1
noninterlace: height/2 - 1
VGA: height - 1
width:
((width * bytes/pixel)/4) - 1
a05f8060: (render_addr1)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Address in VRAM for rendering.
a05f8064: (render_addr2)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Used for strip-buffering but I don't know how this works
a05f8068: (pclip_x)
+-------------------------------+
| 31-27 | 26-16 | 15-11 | 10-0 |
| n/a | max | n/a | min |
+-------------------------------+
Specifies the horizontal pixel clipping area.
a05f806c: (pclip_y)
+-------------------------------+
| 31-27 | 26-16 | 15-11 | 10-0 |
| n/a | max | n/a | min |
+-------------------------------+
Specifies the vertical pixel clipping area.
a05f8074: (shadow)
+----------------------------+
| 31-9 | 8 | 7-0 |
| n/a | enable | intensity |
+----------------------------+
enable:
0: cheap shadow disabled
1: cheap shadow enabled
intensity:
how much cheap shadow should affect polygon depending on
how far away the modifier volume is located
a05f8078: (object_clip)
+--------------+
| 31-0 (FLOAT) |
| distance |
+--------------+
distance:
Position of polygon culling.
a05f807c: (ob_cfg)
+--------------------+
| 31-22 | 21 | 20-0 |
| ??? | ??? | ??? |
+--------------------+
under investigation; write 0x0027df77 for now.
a05f8080:
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x00000007 for now
a05f8084: (tsp_clip)
+--------------+
| 31-0 (FLOAT) |
| distance |
+--------------+
distance:
Position of texture-clipping
a05f8088: (bgplane_z)
+--------------+
| 31-0 (FLOAT) |
| distance |
+--------------+
distance:
Position of background plane.
a05f808c: (bgplane_cfg)
+---------------------------------+
| 31-29 | 28 | 27 |26-24 | 23-0 |
| n/a | ??? | ??? | isp | addr |
+---------------------------------+
(this is probably not 100% correct)
isp:
1: texture disabled
2: texture enabled
3: texture enabled + specular highlight + 16bit UV-coords
4: texture enabled + specular highlight + 32bit UV-coords
addr:
Location of background plane in VRAM.
a05f8098:
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x00800408 for now
a05f80a0: (vram_cfg1)
+----------------+
| 31-8 | 7-0 |
| n/a | refresh |
+----------------+
refresh:
Specifies the refresh-timer for the VRAM.
(normally set to 0x20)
if set to 0 and no read/write cycle is performed
for awhile, VRAM will lose all content.
a05f80a4: (vram_cfg2)
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x0000001f for now
a05f80a8: (vram_cfg3)
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x15d1c951 for now
a05f80b0: (fog_table_col)
+------+
| 31-0 |
| col |
+------+
col:
Colour used for fogging operations on polygons that use
the fogging table.
a05f80b4: (fog_vertex_col)
+------+
| 31-0 |
| col |
+------+
col:
Colour used for fogging operation on polygons that do
manual processing of the fog.
a05f80b8: (fog_density)
+-----------------------------+
| 31-16 | 15-8 | 7-0 |
| n/a | mantissa | exponent |
+-----------------------------+
Specifies a coefficient for TSP fogging.
exponent:
power of 2
a05f80bc: (clamp_max)
+------+
| 31-0 |
| col |
+------+
col:
Colours above this RGB value will be set to this colour.
a05f80c0: (clamp_min)
+------+
| 31-0 |
| col |
+------+
col:
Colours below this RGB value will be set to this colour.
a05f80c4: (gun_pos)
+----------------------------------+
| 31 - 26 | 25 - 16 | 15-10 | 9-0 |
| ??? | vpos | n/a | hpos |
+----------------------------------+
vpos:
Vertical position of lightgun.
hpos:
Horizontal position of lightgun.
a05f80c8: (hpos_irq)
+----------------------+
| 31-28 | 25-16 | 15-0 |
| n/a | pos | ??? |
+----------------------+
pos:
This has to do with VSYNC irq, will perform some more tests
and update accordingly.
note: setting this out-of-range causes _no_ VSYNC IRQs
to be generated so be careful!
a05f80cc: (vpos_irq)
+------------------------------+
| 31-28 | 25-16 | 15-10 | 9-0 |
| n/a | pos1 | n/a | pos2 |
+------------------------------+
pos1 & pos2:
IRQs will be generated when either position is reached by the
rasterbeam.
for PAL:
pos1: 21
pos2: 310
for NTSC, 480 height
pos1: 21
pos2: 258
for NTSC, 240 height
pos1: 21
pos2B: 260
for VGA:
pos1: 21
pos2: 510
a05f80d0: (sync_cfg)
+----------------------------------------------------------------------+
| 31-10 | 9 | 8 | 7-6 | 5 | 4 | 3 | 2 | 1 | 0 |
| n/a | ??? | enable | ??? | ??? | interlace | ??? | HP | VP | ??? |
+----------------------------------------------------------------------+
enable:
0: video output disabled
1: video output enabled
interlace:
0: non-interlace
1: interlace
HP:
0: negative H-sync
1: positive H-sync
VP:
0: negative V-sync
1: positive V-sync
a05f80d4: (hborder)
+-----------------------------+
| 31-28 | 25-16 | 15-10 | 9-0 |
| n/a | start | n/a | end |
+-----------------------------+
Specifies the area of the horizontal border.
for PAL:
start: end:
116 843
for NTSC:
start: end:
126 837
for VGA:
start: end:
126 837
a05f80d8: (sync_load)
+-------------------------------+
| 31-28 | 25-16 | 15-10 | 9-0 |
| n/a | vsync | n/a | hsync |
+-------------------------------+
Specifies the refresh rate of the display.
for PAL, interlace:
vsync: hsync:
624 863
for PAL, noninterlace:
vsync: hsync:
312 863
for NTSC, interlace:
vsync: hsync:
524 857
for NTSC, noninterlace:
vsync: hsync:
262 857
for VGA:
vsync: hsync:
524 857
a05f80dc: (vborder)
+-----------------------------+
| 31-28 | 25-16 | 15-10 | 9-0 |
| n/a | start | n/a | end |
+-----------------------------+
Specifies the area of the vertical border.
for PAL:
start: end:
44 620
for NTSC, 480 height:
start: end:
36 516
for NTSC, 240 height:
start: end:
18 258
for VGA:
start: end:
40 520
a05f80e0: (sync_width)
+---------------------------------------------------------+
| 31-23 | 27-22 | 21-12 | 11-8 | 7 | 6-0 |
| n/a | x | y | vsync-width | n/a | hsync-width |
+---------------------------------------------------------+
Specifies the position(?) and width of the sync pulses.
for PAL, 480 height
x: y: hwidth: vwidth:
0x1f 362 0x05 0x3f
for PAL, 240 height
x: y: Vsync: Hsync:
0x1f 799 0x05 0x3f
for NTSC, 480 height
x: y: Vsync: Hsync:
0x1f 364 0x06 0x3f
for NTSC, 240 height
x: y: Vsync: Hsync:
0x0f 793 0x03 0x3f
for VGA:
x: y: Vsync: Hsync:
0x0f 793 0x03 0x3f
a05f80e4: (tsp_cfg)
+---------------------------------------------+
| 31-19 | 18-16 | 15-13 | 12-8 | 7-5 | 4-0 |
| n/a | ??? | n/a | ??? | n/a | modulo |
+---------------------------------------------+
modulo:
Modulo width for textures.
a05f80e8: (video_cfg)
+--------------------------------------------------------------+
| 31-22 | 21-16 | 15-9 | 8 | 7-4 | 3 | 2 | 1 | 0 |
| n/a | A | n/a | lores | ??? | blank | ??? | ??? | ??? |
+--------------------------------------------------------------+
A:
0x16
lores:
0: 640 width
1: 320 width
blank:
0: normal mode
1: border covers the whole screen
a05f80ec: (hpos)
+-------------+
| 31-10 | 9-0 |
| n/a | pos |
+-------------+
Specifies the horizontal position of the display.
for PAL:
pos:
174
for NTSC:
pos:
164
for VGA:
pos:
144
a05f80f0: (vpos)
+-----------------------------+
| 31-26 | 25-16 | 15-10 | 9-0 |
| n/a | even | n/a | odd |
+-----------------------------+
Specifies the vertical postition of the display for even and odd
fields.
for PAL interlace:
even: odd:
18 18
for PAL noninterlace:
even: odd:
18 17
for NTSC interlace:
even: odd:
18 18
for NTSC non interlace:
even: odd:
18 17
for VGA:
even: odd:
35 35
a05f80f4: (scaler_cfg)
+-------------------------------------+
| 31-19 | 18 | 17 | 16 | 15-0 |
| n/a | ??? | n/a | hscale | vscale |
+-------------------------------------+
hscale:
Horizontal scaler.
vscale:
Vertical scaler.
a05f8108: (palette_cfg)
+---------------+
| 31 - 2 | 1-0 |
| n/a | mode |
+---------------+
mode:
0: ARGB1555
1: RGB565
2: ARGB4444
3: ARGB8888
a05f810c: (sync_stat)
+----------------------------------------------+
| 31-14 | 13 | 12 | 11 | 10 | 9-0 |
| ??? | vblank | hblank | ??? | field | vpos |
+----------------------------------------------+
vblank:
0: normal
1: vblank in progress
hblank:
0: normal
1: hblank in progress
field:
0: odd field of interlace
1: even field of interlace
vpos:
Current vertical position of the rasterbeam.
a05f8110: (???)
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x00093f39 for now
a05f8114: (???)
+------+
| 31-0 |
| ??? |
+------+
under investigation; write 0x00200000 for now
a05f8118: (ta_luminance)
+--------------------+
| 31-16 | 15-8 | 7-0 |
| n/a | b1 | b2 |
+--------------------+
under investigation; write 0x00008040 for now
a05f8124: (ta_opb_start)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Start of Object Pointer Buffer in VRAM (128-byte aligned)
for vertex registration. The Tile Accelerator will examine
vertex data it receives and determine which tiles the objects
might appear in and create links to the object in the
referenced tiles.
a05f8128: (ta_ob_start)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Start of Object Buffer in VRAM (64-bit aligned) for vertex
registration. This is where the vertex data sent to the
Tiling Accelerator will be stored.
a05f812c: (ta_opb_end)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
End of Object Pointer Buffer in VRAM (128-byte aligned) for
vertex registration. The Tiling Accelerator will not use
memory beyond this point when creating Object Links. the
Object Pointer Buffer grows downwards in memory so this
address should be located before the start address.
a05f8130: (ta_ob_end)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
End of Object Buffer in VRAM (64-bit aligned) for vertex
registration. the Tiling Accelerator will not use memory
beyond this point when receiving data.
a05f8134: (ta_opb_pos)
+--------------+
| 31-23 | 22-0 |
| n/a | addr |
+--------------+
addr:
Object Pointer Buffer position
This register contains the current address to be used by
the Object Pointer Buffer when more space needs to be
allocated.
a05f8138: (ta_ob_pos)
+--------------+
| 31-23 | 22-0 |
| n/a | addr |
+--------------+
addr:
Object Buffer position
This register contains the current address to be used by
the Object Buffer when Tile Accelerator receives vertex data.
a05f813c: (tilebuf_size)
+----------------+
| 31-16 | 15-0 |
| height | width |
+----------------+
height:
Height of tile buffer in 32-pixel high tiles, minus 1.
width:
Width of tile buffer in 32-pixel wide tiles, minus 1.
a05f8140: (ta_opb_cfg)
+---------------------------------------------------------------------
| 31-21 | 20 | 19-18 | 17-16 | 15-14 | 13-12 | 11-10 |
| n/a | unknown | n/a | punch-through | n/a | transmod | n/a |
+---------------------------------------------------------------------
-------------------------------------------------------+
| 9-8 | 7-6 | 5-4 | 3 | 2 | 1-0 |
| transpoly | n/a | opaquemod | n/a | ??? | opaquepoly |
-------------------------------------------------------+
unknown:
Set to 1 for now.
punch-through:
0: size_0 - Punch-through Polygons disabled
1: size_8 - 7 Object Pointers + 1 List Pointer
2: size_16 - 15 Object Pointers + 1 List Pointer
3: size_32 - 31 Object Pointers + 1 List Pointer
transmod:
0: size_0 - Translucent Modifiers disabled
1: size_8 - 7 Object Pointers + 1 List Pointer
2: size_16 - 15 Object Pointers + 1 List Pointer
3: size_32 - 31 Object Pointers + 1 List Pointer
transpoly:
0: size_0 - Translucent Polygons disabled
1: size_8 - 7 Object Pointers + 1 List Pointer
2: size_16 - 15 Object Pointers + 1 List Pointer
3: size_32 - 31 Object Pointers + 1 List Pointer
opaquemod:
0: size_0 - Opaque Modifiers disabled
1: size_8 - 7 Object Pointers + 1 List Pointer
2: size_16 - 15 Object Pointers + 1 List Pointer
3: size_32 - 31 Object Pointers + 1 List Pointer
opaquepoly:
0: size_0 - Opaque Polygons disabled
1: size_8 - 7 Object Pointers + 1 List Pointer
2: size_16 - 15 Object Pointers + 1 List Pointer
3: size_32 - 31 Object Pointers + 1 List Pointer
a05f8144: (ta_init)
+-------------+
| 31 | 30-0 |
| init | n/a |
+-------------+
init:
0: normal
1: initialize TA vertex registration parameters
a05f8148: (yuv_addr)
+--------------+
| 31-24 | 23-0 |
| n/a | addr |
+--------------+
addr:
Destination address in VRAM (32-byte aligned) for YUV
conversion.
a05f814c: (yuv_cfg1)
+-----------------------------------------------------------+
| 31-25 | 24 | 23-17 | 16 | 15-14 | 13-8 | 7-6 | 5-0 |
| n/a | mode | n/a | ??? | n/a | height | n/a | width |
+-----------------------------------------------------------+
mode:
0: YUV422
1: YUV420
height:
Height in 16x16-pixel blocks.
width:
Width in 16x16-pixel blocks.
a05f8150: (yuv cfg2)
+------+
| 31-0 |
| ??? |
+------+
under investigation
a05f8160: (???)
+------+
| 31-0 |
| ??? |
+------+
under investigation
a05f8164: (ta_opl_init)
+--------------+
| 31-24 | 23-0 |
| ??? | addr |
+--------------+
addr:
Start of Object Pointer List allocation in VRAM
(128-byte aligned). The Object Pointer List is part
of the Object Pointer Buffer and this is where the Tile
Accelerator allocating memory if needed for the Object
Pointer Buffer. The allocating is performed downwards in
memory and will cease when passing the address indicated
in register ta_opb_end (a05f812c).
(maybe this is actually some sort of initializing
because writing a different address from the one specified
in ta_opb_start doesnt seem to work....)
a05f8180:
+------+
| 31-0 |
| ??? |
+------+
a05f8184:
+------+
| 31-0 |
| ??? |
+------+
a05f8190:
+------+
| 31-0 |
| ??? |
+------+
a05f8194:
+------+
| 31-0 |
| ??? |
+------+
a05f8198:
+------+
| 31-0 |
| ??? |
+------+
a05f8200 - a05f85ff: (fog_table)
+--------------+
| 63-0 (FLOAT) |
| fog entry |
+--------------+
128 entries for use with fogging operations. The index of the table
is used as a depth-value and the element at that position is used to
specify a fog density. Polygons using fog_table will use the fog
density as the alpha value of the fog. Polygons that use fog_table2
change the polygon colour to the fog density value and the polygon
alpha value will become the fog alpha value.
a05f8600 - a05f8fff: (opl_table)
+------+
| 31-0 |
| ??? |
+------+
This is quite likely where the Tile Accelerator stores pointers to
the current addresses in the Object Pointer List segments.
a05f9000 - a05f9fff: (palette_table)
+---------------+
| 31-0 |
| palette entry |
+---------------+
1024 entries for use with palettized textures. Palette is split into
banks depending on colour mode. For 4bpp mode there are 64 banks
with 16 colours in each; for 8bpp mode there are 4 banks with 256
colours in each.
Notes:
Some uncertainties still linger, but this doc is a bit more correct than
the previous. Everything is unoffical though and should be taken for what it
is; only an attempt at understanding the workings of a complex chip. It is
not yet complete and most certainly contains errors in some parts, but I feel
somewhat confident that it is correct in at least an equal amount :-)
Reach me at: jlo@ludd.luth.se for any questions, comments or corrections...
-Lars Olsson
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