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design example: RTL8019AS LAN Adapter (non compatible HIT-0300) (part 1)
The original article, written by jj1odm, is available at http://jj1odm.sizious.com/
spec of RTL8019AS LAN Adapter:
used device:
XC9572XL-VQ44: G2 bus interface logic
RTL8019AS: lan controller chip
74LVX245: 3.3v 5v buffer
93C46: MAC address and config data eeprom
device mapping: (byte access only)
0xb4000040 - 0xb400007e: RTL8019AS registers {even address} (lower byte mapping)
0xb4000041: ID code 1 register '0x80' {read only} (upper byte mapping)
0xb4000043: ID code 2 register '0x19' {read only} (upper byte mapping)
0xb400007f: control register {read/write} (upper byte mapping)
bit[7] interrupt enable {active high} (read/write)
bit[6] interrupt status {active high} (read only)
bit[5:1] not use {read always '00000'}
bit[0] reset {active high} (read/write)
interrupt: use /IRQA
device access time: 200nSEC (use /BTA /BTB control)
(When RTL8019AS is accessed, it is extended by the state of 'IOCHRDY' terminal.)
lan adapter circuit
cpld internal ciucuit
g2lanadp8019.v
// $$$ : g2lanadp8019.v -- RTL8019AS lan adaptor for G2 bus.
//
// used circuit: lanadp8019.gif
// used device: XC9572XL-VQ44 (Xilinx)
// last update: 2007/3/15
//
// device mapping: (byte access only)
// base address + 0x00 .. 0x3e: RTL8019AS registers {even address} (lower byte mapping)
// base address + 1: ID code 1 register '0x80' {read only} (upper byte mapping)
// base address + 3: ID code 2 register '0x19' {read only} (upper byte mapping)
// base address + 0x3f: control register {read/write} (upper byte mapping)
// bit[7] : interrupt enable {active high} (read/write)
// bit[6] : interrupt status {active high} (read only)
// bit[5:1] : not use {read always '00000'}
// bit[0] : reset {active high} (read/write)
//
//
// date 2007/1/21 designed by jj1odm
`timescale 1ns / 1ps
module g2lanadp8019(
input clk, // G2 bus system clock (25MHz)
input aen, // G2 bus address enable (active low)
input lben, // G2 bus direction and lower byte enable (active low) [change name: dir => lben]
input uben, // G2 bus upper byte enable (active low) [change name: den => uben]
inout [15:0] ad, // G2 bus address/data multiplexed bus (16 bit)
output btan, // G2 bus bus termination A (active low)
output btbn, // G2 bus bus termination B (active low)
output irqn, // G2 bus interrupt (open drain active low)
input resetn, // G2 bus reset (active low)
output [4:0] sa, // RTL8019AS SA4 .. SA0: register address
output iorn, // RTL8019AS IORB: I/O read strobe (active low)
output iown, // RTL8019AS IOWB: I/O write strobe (active low)
input int0, // RTL8019AS INT0: interrupt (active high)
input iochrdy, // RTL8019AS IOCHRDY: bus wait ccontrol (active low)
output rstdrv // RTL8019AS RSTDRV: chip reset (active high)
);
parameter IOBASE_HIGH = 13'h1400; // I/O base high word address
parameter IOBASE_LOW = 10'b0000000001; // I/O base low word address
parameter ID_CODE_1 = 8'h80; // this adaptor ID code 1 (RTL'80'19AS)
parameter ID_CODE_2 = 8'h19; // this adaptor ID code 2 (RTL80'19'AS)
parameter G2_IDLE = 2'b00; // G2 bus idle state
parameter G2_HI_ADDRESS = 2'b01; // G2 bus high address state
parameter G2_DATA = 2'b11; // G2 bus data state
parameter G2_END = 2'b10; // G2 bus end state
parameter ACCESS_WIDTH = 3; // bus access width (ACCESS_WIDTH * 40nSEC) + 160nSEC
reg int_enable = 1'b0; // interrupt enable flipflop (init 0)
reg reset_ff = 1'b0; // reset flipflop (init 0)
reg [1:0] g2bus_state = G2_IDLE; // G2 bus state machine register (init G2_IDLE state)
reg aen_old = 1'b1; // G2 bus cycle detect register (init '1')
reg [3:0] wait_cnt = 4'b0000; // G2 bus wait counter (init 0)
reg bus_end = 1'b1; // bus end flag (active low)
reg [15:0] g2reg; // for g2 bus tri-state logic
reg [4:0] adrs; // SA[4:0] address latch register (5bit)
reg direction; // direction latch register
wire bus_valid; // bus cycle valid flag node
wire [7:0] status_node; // status node
// 'irqn' siganl assign
assign irqn = (int_enable & int0) ? 1'b0 : 1'bz; // assign 'irqn'
// 'rstdrv' siganl assign
assign rstdrv = ~resetn | reset_ff; // assign 'rstdrv'
// status node assign (control register)
assign status_node[7] = int_enable;
assign status_node[6] = int0;
assign status_node[5:1] = 5'b00000;
assign status_node[0] = reset_ff;
// G2 bus termination control A/B (for byte access)
assign btan = g2bus_state == G2_END ? bus_end : 1'bz;
assign btbn = g2bus_state == G2_END ? bus_end : 1'bz;
// RTL8019AS interface node (lower byte access)
assign bus_valid = g2bus_state == G2_DATA | g2bus_state == G2_END; // bus valid flag
assign sa = adrs; // RTL8019AS 'SA[4:0]'
assign iorn = ~(direction & ~lben & uben & bus_valid); // RTL8019AS 'iorn'
assign iown = ~(~direction & ~lben & uben & bus_valid); // RTL8019AS 'iown'
// G2 bus tri-state buffer & ID code & control register logic (upper byte access)
assign ad = g2reg;
always @(resetn or bus_valid or uben or lben or direction or adrs or ad or status_node) begin
if (resetn) begin
if (bus_valid & ~uben & lben) begin // upper byte access
if (adrs[4:1] == 4'b0000) begin // ID register 1/2
if (direction) begin // read
g2reg[7:0] < = 8'hzz;
g2reg[15:8] < = adrs[0] == 1'b0 ? ID_CODE_1 : ID_CODE_2; // read ID code 1/2
end
else begin // write
g2reg < = 16'hzzzz;
end
end
else begin // control register
if (direction) begin // read
g2reg[7:0] < = 8'hzz;
g2reg[15:8] < = status_node; // read control register (status_node)
end
else begin // write
g2reg < = 16'hzzzz;
int_enable < = ad[15]; // write interrupt enable f/f
reset_ff < = ad[8]; // write reset f/f
end
end
end
else g2reg < = 16'hzzzz;
end
else begin // resetn == 0 then
g2reg < = 16'hzzzz;
reset_ff < = 1'b0; // init reset_ff (reset bit off)
int_enable < = 1'b0; // init int_enable (interrupt disable)
end
end
// G2 bus state machine (ignore: not this device or long word access)
always @(posedge clk or negedge resetn) begin
if (~resetn) begin
g2bus_state < = G2_IDLE; // init 'g2bus_state'
aen_old < = 1'b1; // init 'aen_old'
bus_end < = 1'b1; // init 'bus_end'
end
else begin
aen_old < = aen; // for negtive edge detect 'aen'
// idle state
if (g2bus_state == G2_IDLE) begin
// negtive edge detect 'aen' & equal IOBASE_LOW
if (~aen & aen_old & ad[15:6] == IOBASE_LOW) begin
adrs < = ad[5:1]; // SA[4:0] (low word address) latch
direction < = lben; // direcion latch
wait_cnt < = 4'b0000; // init wait count
bus_end < = 1'b1; // init bus end flag
g2bus_state < = G2_HI_ADDRESS; // next state
end
end
// high address state
if (g2bus_state == G2_HI_ADDRESS) begin
if (ad[12:0] == IOBASE_HIGH) g2bus_state < = G2_DATA; // this device then next state
else g2bus_state < = G2_IDLE; // else return idle state
end
// data state
if (g2bus_state == G2_DATA) begin
if (~aen | (lben & uben)) g2bus_state < = G2_IDLE; // long access or wait timeout then return idle state
else begin // normal bus access
wait_cnt < = iochrdy ? wait_cnt + 4'b0001 : ACCESS_WIDTH - 2;
if (wait_cnt == ACCESS_WIDTH) begin // check bus wait count
bus_end < = 1'b0; // bus_end active low
g2bus_state < = G2_END; // next state
end
end
end
// bus end state (for bus end pulse)
if (g2bus_state == G2_END) begin
bus_end < = 1'b1; // 1 clock bus_end high
if (bus_end) begin // for fast rising edge (guard of hi-z)
g2bus_state < = G2_IDLE; // return idle state
end
end
end
end
endmodule
// end of : g2lanadp8019.v
g2lanadp8019.ucf
// Template UCF file created by the Project Navigator
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
NET "rstdrv" LOC = "P22" ;
NET "ad< 0>" LOC = "P30" ;
NET "ad< 10>" LOC = "P41" ;
NET "ad< 11>" LOC = "P42" ;
NET "ad< 12>" LOC = "P43" ;
NET "ad< 13>" LOC = "P44" ;
NET "ad< 14>" LOC = "P2" ;
NET "ad< 15>" LOC = "P3" ;
NET "ad< 1>" LOC = "P31" ;
NET "ad< 2>" LOC = "P32" ;
NET "ad< 3>" LOC = "P33" ;
NET "ad< 4>" LOC = "P34" ;
NET "ad< 5>" LOC = "P36" ;
NET "ad< 6>" LOC = "P37" ;
NET "ad< 7>" LOC = "P38" ;
NET "ad< 8>" LOC = "P39" ;
NET "ad< 9>" LOC = "P40" ;
NET "aen" LOC = "P5" ;
NET "clk" LOC = "P1" ;
NET "iochrdy" LOC = "P29" ;
NET "btbn" LOC = "P21" ;
NET "btan" LOC = "P20" ;
NET "resetn" LOC = "P19" ;
NET "sa< 0>" LOC = "P18" ;
NET "sa< 1>" LOC = "P16" ;
NET "sa< 2>" LOC = "P14" ;
NET "sa< 3>" LOC = "P13" ;
NET "sa< 4>" LOC = "P12" ;
NET "uben" LOC = "P6" ;
NET "lben" LOC = "P7" ;
NET "int0" LOC = "P23" ;
NET "irqn" LOC = "P8" ;
NET "iorn" LOC = "P28" ;
NET "iown" LOC = "P27" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
cpld fuse data
g2lanadp8019.jed
Programmer Jedec Bit Map
Date Extracted: Fri Apr 13 21:09:21 2007
QF46656*
QP44*
QV0*
F0*
X0*
J0 0*
N DEVICE XC9572XL-5-VQ44*
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N PPMAP 49 13*
N PPMAP 50 14*
N PPMAP 52 16*
N PPMAP 59 18*
N PPMAP 62 19*
N PPMAP 26 2*
N PPMAP 63 20*
N PPMAP 65 21*
N PPMAP 68 22*
N PPMAP 72 23*
N PPMAP 82 27*
N PPMAP 83 28*
N PPMAP 87 29*
N PPMAP 27 3*
N PPMAP 88 30*
N PPMAP 89 31*
N PPMAP 90 32*
N PPMAP 92 33*
N PPMAP 3 34*
N PPMAP 7 36*
N PPMAP 9 37*
N PPMAP 10 38*
N PPMAP 11 39*
N PPMAP 12 40*
N PPMAP 13 41*
N PPMAP 15 42*
N PPMAP 20 43*
N PPMAP 21 44*
N PPMAP 29 5*
N PPMAP 31 6*
N PPMAP 33 7*
N PPMAP 38 8*
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L0046480 00000000 00000100 00000000 00000000*
L0046512 000000 000000 000000 001010*
L0046536 000000 000001 000000 000001*
L0046560 000000 000001 000001 000001*
L0046584 000000 000000 000000 000001*
L0046608 000000 000001 000001 000000*
L0046632 000000 000001 000001 000001*
C15A1*
17AA
content of 93C46 memory
=======================
Content of 93C46 memory
=======================
Config data 1 to 4:
address 0(word): 00 80 .. (CONFIG2, CONFIG1)
address 1(word): 00 10 .. (CONFIG4, CONFIG3)
MAC address data: XXXX XXXX XXXX (ex. 01:23:45:67:89:AB)
address 2(word): XXXX .. (0x2301)
address 3(word): XXXX .. (0x6745)
address 4(word): XXXX .. (0xAB89)
product ID etc.:
address 5 - 8(word): 0000
98C46 memory dump: (word dump)
____ ____ ____
00: 0080 0010 XXXX XXXX XXXX 0000 0000 0000
08: 0000 FFFF FFFF FFFF FFFF FFFF FFFF FFFF
..
all 0xFFFF
..
38: FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
Please change the MAC address data of 'XXXX' and write
the content of the above-mentioned memory dump in 93C46.
dcload-ip 1.0.4 target binary
readme.txt
dcload-ip 1.0.4 target (Dreamcast) binary for RTL8019AS Lan Adapter
--------------------------------------------------------------------
It is dcload-ip 1.0.4 corresponding to RTL8019AS Lan Adapter.
(When starting, HIT-0400/HIT-0300/RTL8019AS lan adapter 3 kind of
LAN adapter is judged automatically. )
Content of archive file:
ip.bin -------- for make CD
1st_read.bin -- (scrambled) for make CD
1st_read.srec - for sirial upload.
readme.txt ---- this text
Default IP is '192.168.1.234'
(Please search and rewrite the character string of
"192.168.1.234" when changing. )
by jj1odm
reference picture
