Dreamcast Memory organization
@Dreamcast
Published in
Dreamcast technical
· 21 Dec 2018
Dreamcast main memory subsystem v1.2, 2001-03-15 Note: Table 3.2.1 contains the essential timing figures. Remember that the cycles given are buscycles (100MHz), not SH4 core cycles! Table of Contents 0. Introduction 0.1 Quickstart 1. Dreamcast main memory configuration 2. SDRAM operation 2.1 Overview. Figure 2.1.1: Model of an SDRAM chip 2.2 Commands 2.3 Read / write access 2.4 Aborting and pipelining bus transactions 3. SDRAM in the Dreamcast 3.1 Access philosophy 3.2 Access timing in RASDown mode Table 3.2.1: Common access timings Figure 3.2.1: CPU burst read, no row active Figure 3.2.2: CPU burst read, row hit Figure 3.2.3: CPU bur...